1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ 3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s 4# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \ 5# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s 6 7--- 8name: rotl_i32 9legalized: true 10regBankSelected: true 11body: | 12 bb.0: 13 liveins: $x10, $x11 14 15 ; CHECK-LABEL: name: rotl_i32 16 ; CHECK: liveins: $x10, $x11 17 ; CHECK-NEXT: {{ $}} 18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 19 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 20 ; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]] 21 ; CHECK-NEXT: $x10 = COPY [[ROL]] 22 ; CHECK-NEXT: PseudoRET implicit $x10 23 %0:gprb(s32) = COPY $x10 24 %1:gprb(s32) = COPY $x11 25 %2:gprb(s32) = G_ROTL %0, %1(s32) 26 $x10 = COPY %2(s32) 27 PseudoRET implicit $x10 28 29... 30--- 31name: rotr_i32 32legalized: true 33regBankSelected: true 34body: | 35 bb.0: 36 liveins: $x10, $x11 37 38 ; CHECK-LABEL: name: rotr_i32 39 ; CHECK: liveins: $x10, $x11 40 ; CHECK-NEXT: {{ $}} 41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 42 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 43 ; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]] 44 ; CHECK-NEXT: $x10 = COPY [[ROR]] 45 ; CHECK-NEXT: PseudoRET implicit $x10 46 %0:gprb(s32) = COPY $x10 47 %1:gprb(s32) = COPY $x11 48 %2:gprb(s32) = G_ROTR %0, %1(s32) 49 $x10 = COPY %2(s32) 50 PseudoRET implicit $x10 51 52... 53--- 54name: rotl_imm_i32 55legalized: true 56regBankSelected: true 57body: | 58 bb.0: 59 liveins: $x10 60 61 ; CHECK-LABEL: name: rotl_imm_i32 62 ; CHECK: liveins: $x10 63 ; CHECK-NEXT: {{ $}} 64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 65 ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 27 66 ; CHECK-NEXT: $x10 = COPY [[RORI]] 67 ; CHECK-NEXT: PseudoRET implicit $x10 68 %0:gprb(s32) = COPY $x10 69 %1:gprb(s32) = G_CONSTANT i32 5 70 %2:gprb(s32) = G_ROTL %0, %1(s32) 71 $x10 = COPY %2(s32) 72 PseudoRET implicit $x10 73 74... 75--- 76name: rotr_imm_i32 77legalized: true 78regBankSelected: true 79body: | 80 bb.0: 81 liveins: $x10 82 83 ; CHECK-LABEL: name: rotr_imm_i32 84 ; CHECK: liveins: $x10 85 ; CHECK-NEXT: {{ $}} 86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 87 ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 5 88 ; CHECK-NEXT: $x10 = COPY [[RORI]] 89 ; CHECK-NEXT: PseudoRET implicit $x10 90 %0:gprb(s32) = COPY $x10 91 %1:gprb(s32) = G_CONSTANT i32 5 92 %2:gprb(s32) = G_ROTR %0, %1(s32) 93 $x10 = COPY %2(s32) 94 PseudoRET implicit $x10 95 96... 97