xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir (revision 65f946cba4085d3d3054a0db3ed0e4006b6cf783) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
3# RUN: -verify-machineinstrs %s -o - | FileCheck %s
4---
5name:            add_i32
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0.entry:
11    liveins: $x10, $x11
12
13    ; CHECK-LABEL: name: add_i32
14    ; CHECK: liveins: $x10, $x11
15    ; CHECK-NEXT: {{  $}}
16    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
17    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
18    ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
19    ; CHECK-NEXT: $x10 = COPY [[ADD]]
20    ; CHECK-NEXT: PseudoRET implicit $x10
21    %0:gprb(p0) = COPY $x10
22    %1:gprb(s32) = COPY $x11
23    %2:gprb(p0) = G_PTR_ADD %0, %1
24    $x10 = COPY %2(p0)
25    PseudoRET implicit $x10
26
27...
28---
29name:            addi_i32
30legalized:       true
31regBankSelected: true
32tracksRegLiveness: true
33body:             |
34  bb.0.entry:
35    liveins: $x10, $x11
36
37    ; CHECK-LABEL: name: addi_i32
38    ; CHECK: liveins: $x10, $x11
39    ; CHECK-NEXT: {{  $}}
40    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
41    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 20
42    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
43    ; CHECK-NEXT: PseudoRET implicit $x10
44    %0:gprb(p0) = COPY $x10
45    %1:gprb(s32) = G_CONSTANT i32 20
46    %2:gprb(p0) = G_PTR_ADD %0, %1
47    $x10 = COPY %2(p0)
48    PseudoRET implicit $x10
49
50...
51