xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir (revision cc9ba5600e540fd4e059d20591917962a6df043d)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
3# RUN: | FileCheck -check-prefix=RV32I %s
4
5---
6name:            phi_i32
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  ; RV32I-LABEL: name: phi_i32
12  ; RV32I: bb.0:
13  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
14  ; RV32I-NEXT: {{  $}}
15  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
16  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
17  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x12
18  ; RV32I-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
19  ; RV32I-NEXT:   BNE [[ANDI]], $x0, %bb.2
20  ; RV32I-NEXT:   PseudoBR %bb.1
21  ; RV32I-NEXT: {{  $}}
22  ; RV32I-NEXT: bb.1:
23  ; RV32I-NEXT: {{  $}}
24  ; RV32I-NEXT: bb.2:
25  ; RV32I-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0
26  ; RV32I-NEXT:   $x10 = COPY [[PHI]]
27  ; RV32I-NEXT:   PseudoRET implicit $x10
28  bb.0:
29    liveins: $x10, $x11, $x12
30
31    %0:gprb(s32) = COPY $x10
32    %1:gprb(s32) = COPY $x11
33    %2:gprb(s32) = COPY $x12
34    %3:gprb(s32) = G_CONSTANT i32 1
35    %4:gprb(s32) = G_AND %0, %3
36    G_BRCOND %4(s32), %bb.2
37    G_BR %bb.1
38
39  bb.1:
40
41  bb.2:
42    %5:gprb(s32) = G_PHI %2(s32), %bb.1, %1(s32), %bb.0
43    $x10 = COPY %5(s32)
44    PseudoRET implicit $x10
45
46...
47---
48name:            phi_ptr
49legalized:       true
50regBankSelected: true
51tracksRegLiveness: true
52body:             |
53  ; RV32I-LABEL: name: phi_ptr
54  ; RV32I: bb.0.entry:
55  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
56  ; RV32I-NEXT: {{  $}}
57  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
58  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
59  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x12
60  ; RV32I-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
61  ; RV32I-NEXT:   BNE [[ANDI]], $x0, %bb.2
62  ; RV32I-NEXT:   PseudoBR %bb.1
63  ; RV32I-NEXT: {{  $}}
64  ; RV32I-NEXT: bb.1:
65  ; RV32I-NEXT: {{  $}}
66  ; RV32I-NEXT: bb.2:
67  ; RV32I-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0
68  ; RV32I-NEXT:   $x10 = COPY [[PHI]]
69  ; RV32I-NEXT:   PseudoRET implicit $x10
70  bb.0.entry:
71    liveins: $x10, $x11, $x12
72
73    %0:gprb(s32) = COPY $x10
74    %1:gprb(p0) = COPY $x11
75    %2:gprb(p0) = COPY $x12
76    %3:gprb(s32) = G_CONSTANT i32 1
77    %4:gprb(s32) = G_AND %0, %3
78    G_BRCOND %4(s32), %bb.2
79    G_BR %bb.1
80
81  bb.1:
82
83  bb.2:
84    %5:gprb(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0
85    $x10 = COPY %5(p0)
86    PseudoRET implicit $x10
87
88...
89