xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir (revision 581fd2fa573e39607ea164c0b4a8057baeb62c69) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
3# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4
5---
6name:            sitofp_s16_s32
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.0:
12    liveins: $x10
13
14    ; CHECK-LABEL: name: sitofp_s16_s32
15    ; CHECK: liveins: $x10
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18    ; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
19    ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
20    ; CHECK-NEXT: PseudoRET implicit $f10_h
21    %0:gprb(s32) = COPY $x10
22    %1:fprb(s16) = G_SITOFP %0(s32)
23    $f10_h = COPY %1(s16)
24    PseudoRET implicit $f10_h
25
26...
27---
28name:            uitofp_s16_s32
29legalized:       true
30regBankSelected: true
31tracksRegLiveness: true
32body:             |
33  bb.0:
34    liveins: $x10
35
36    ; CHECK-LABEL: name: uitofp_s16_s32
37    ; CHECK: liveins: $x10
38    ; CHECK-NEXT: {{  $}}
39    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
40    ; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
41    ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
42    ; CHECK-NEXT: PseudoRET implicit $f10_h
43    %0:gprb(s32) = COPY $x10
44    %1:fprb(s16) = G_UITOFP %0(s32)
45    $f10_h = COPY %1(s16)
46    PseudoRET implicit $f10_h
47
48...
49