xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir (revision 6976dac09db6dab3ef9eb68f1d19b70aa2847773) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
3# RUN: | FileCheck -check-prefix=RV32F %s
4
5---
6name:            implicit_def_gpr
7legalized:       true
8regBankSelected: true
9body:             |
10  bb.0:
11    ; RV32F-LABEL: name: implicit_def_gpr
12    ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
13    ; RV32F-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]]
14    ; RV32F-NEXT: $x10 = COPY [[ADD]]
15    %0:gprb(s32) = G_IMPLICIT_DEF
16    %1:gprb(s32) = G_ADD %0, %0
17    $x10 = COPY %1(s32)
18...
19---
20name:            implicit_def_copy_gpr
21legalized:       true
22regBankSelected: true
23body:             |
24  bb.0:
25    ; RV32F-LABEL: name: implicit_def_copy_gpr
26    ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
27    ; RV32F-NEXT: $x10 = COPY [[DEF]]
28    %0:gprb(s32) = G_IMPLICIT_DEF
29    %1:gprb(s32) = COPY %0(s32)
30    $x10 = COPY %1(s32)
31...
32
33---
34name:            implicit_def_fpr
35legalized:       true
36regBankSelected: true
37body:             |
38  bb.0:
39    ; RV32F-LABEL: name: implicit_def_fpr
40    ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF
41    ; RV32F-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[DEF]], [[DEF]], 7
42    ; RV32F-NEXT: $f10_f = COPY [[FADD_S]]
43    %0:fprb(s32) = G_IMPLICIT_DEF
44    %1:fprb(s32) = G_FADD %0, %0
45    $f10_f = COPY %1(s32)
46...
47---
48name:            implicit_def_copy_fpr
49legalized:       true
50regBankSelected: true
51body:             |
52  bb.0:
53    ; RV32F-LABEL: name: implicit_def_copy_fpr
54    ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF
55    ; RV32F-NEXT: $f10_f = COPY [[DEF]]
56    %0:fprb(s32) = G_IMPLICIT_DEF
57    %1:fprb(s32) = COPY %0(s32)
58    $f10_f = COPY %1(s32)
59...
60