xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir (revision 581fd2fa573e39607ea164c0b4a8057baeb62c69) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
3# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4
5---
6name:            fptosi_s32_s16
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.1:
12    liveins: $f10_h
13
14    ; CHECK-LABEL: name: fptosi_s32_s16
15    ; CHECK: liveins: $f10_h
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
18    ; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1
19    ; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]]
20    ; CHECK-NEXT: PseudoRET implicit $x10
21    %0:fprb(s16) = COPY $f10_h
22    %1:gprb(s32) = G_FPTOSI %0(s16)
23    $x10 = COPY %1(s32)
24    PseudoRET implicit $x10
25
26...
27---
28name:            fptoui_s32_s16
29legalized:       true
30regBankSelected: true
31tracksRegLiveness: true
32body:             |
33  bb.1:
34    liveins: $f10_h
35
36    ; CHECK-LABEL: name: fptoui_s32_s16
37    ; CHECK: liveins: $f10_h
38    ; CHECK-NEXT: {{  $}}
39    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
40    ; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1
41    ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]]
42    ; CHECK-NEXT: PseudoRET implicit $x10
43    %0:fprb(s16) = COPY $f10_h
44    %1:gprb(s32) = G_FPTOUI %0(s16)
45    $x10 = COPY %1(s32)
46    PseudoRET implicit $x10
47
48...
49