1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 2# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \ 3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32 4# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \ 5# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64 6 7--- 8name: half_imm 9legalized: true 10regBankSelected: true 11body: | 12 bb.1: 13 ; RV32-LABEL: name: half_imm 14 ; RV32: [[LUI:%[0-9]+]]:gpr = LUI 4 15 ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 584 16 ; RV32-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDI]] 17 ; RV32-NEXT: $f10_h = COPY [[FMV_H_X]] 18 ; RV32-NEXT: PseudoRET implicit $f10_h 19 ; 20 ; RV64-LABEL: name: half_imm 21 ; RV64: [[LUI:%[0-9]+]]:gpr = LUI 4 22 ; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 584 23 ; RV64-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDIW]] 24 ; RV64-NEXT: $f10_h = COPY [[FMV_H_X]] 25 ; RV64-NEXT: PseudoRET implicit $f10_h 26 %0:fprb(s16) = G_FCONSTANT half 0xH4248 27 $f10_h = COPY %0(s16) 28 PseudoRET implicit $f10_h 29 30... 31--- 32name: half_imm_op 33legalized: true 34regBankSelected: true 35body: | 36 bb.1: 37 liveins: $f10_h 38 39 ; CHECK-LABEL: name: half_imm_op 40 ; CHECK: liveins: $f10_h 41 ; CHECK-NEXT: {{ $}} 42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h 43 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 15 44 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 10 45 ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[SLLI]] 46 ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[FMV_H_X]], 7 47 ; CHECK-NEXT: $f10_h = COPY [[FADD_H]] 48 ; CHECK-NEXT: PseudoRET implicit $f10_h 49 %0:fprb(s16) = COPY $f10_h 50 %1:fprb(s16) = G_FCONSTANT half 1.000000e+00 51 %2:fprb(s16) = G_FADD %0, %1 52 $f10_h = COPY %2(s16) 53 PseudoRET implicit $f10_h 54 55... 56--- 57name: half_positive_zero 58legalized: true 59regBankSelected: true 60body: | 61 bb.1: 62 liveins: $x10 63 64 ; CHECK-LABEL: name: half_positive_zero 65 ; CHECK: liveins: $x10 66 ; CHECK-NEXT: {{ $}} 67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 68 ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[COPY]] 69 ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]] 70 ; CHECK-NEXT: PseudoRET implicit $f10_h 71 %1:fprb(s16) = G_FCONSTANT half 0.000000e+00 72 $f10_h = COPY %1(s16) 73 PseudoRET implicit $f10_h 74 75... 76--- 77name: half_negative_zero 78legalized: true 79regBankSelected: true 80body: | 81 bb.1: 82 liveins: $x10 83 84 ; CHECK-LABEL: name: half_negative_zero 85 ; CHECK: liveins: $x10 86 ; CHECK-NEXT: {{ $}} 87 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1048568 88 ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[LUI]] 89 ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]] 90 ; CHECK-NEXT: PseudoRET implicit $f10_h 91 %1:fprb(s16) = G_FCONSTANT half -0.000000e+00 92 $f10_h = COPY %1(s16) 93 PseudoRET implicit $f10_h 94 95... 96