1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ 3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s 4# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ 5# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s 6 7--- 8name: fadd_f32 9legalized: true 10regBankSelected: true 11tracksRegLiveness: true 12body: | 13 bb.0: 14 liveins: $f10_f, $f11_f 15 16 ; CHECK-LABEL: name: fadd_f32 17 ; CHECK: liveins: $f10_f, $f11_f 18 ; CHECK-NEXT: {{ $}} 19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 20 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 21 ; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[COPY1]], 7 22 ; CHECK-NEXT: $f10_f = COPY [[FADD_S]] 23 ; CHECK-NEXT: PseudoRET implicit $f10_f 24 %0:fprb(s32) = COPY $f10_f 25 %1:fprb(s32) = COPY $f11_f 26 %2:fprb(s32) = G_FADD %0, %1 27 $f10_f = COPY %2(s32) 28 PseudoRET implicit $f10_f 29 30... 31--- 32name: fsub_f32 33legalized: true 34regBankSelected: true 35tracksRegLiveness: true 36body: | 37 bb.0: 38 liveins: $f10_f, $f11_f 39 40 ; CHECK-LABEL: name: fsub_f32 41 ; CHECK: liveins: $f10_f, $f11_f 42 ; CHECK-NEXT: {{ $}} 43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 44 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 45 ; CHECK-NEXT: [[FSUB_S:%[0-9]+]]:fpr32 = nofpexcept FSUB_S [[COPY]], [[COPY1]], 7 46 ; CHECK-NEXT: $f10_f = COPY [[FSUB_S]] 47 ; CHECK-NEXT: PseudoRET implicit $f10_f 48 %0:fprb(s32) = COPY $f10_f 49 %1:fprb(s32) = COPY $f11_f 50 %2:fprb(s32) = G_FSUB %0, %1 51 $f10_f = COPY %2(s32) 52 PseudoRET implicit $f10_f 53 54... 55--- 56name: fmul_f32 57legalized: true 58regBankSelected: true 59tracksRegLiveness: true 60body: | 61 bb.0: 62 liveins: $f10_f, $f11_f 63 64 ; CHECK-LABEL: name: fmul_f32 65 ; CHECK: liveins: $f10_f, $f11_f 66 ; CHECK-NEXT: {{ $}} 67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 68 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 69 ; CHECK-NEXT: [[FMUL_S:%[0-9]+]]:fpr32 = nofpexcept FMUL_S [[COPY]], [[COPY1]], 7 70 ; CHECK-NEXT: $f10_f = COPY [[FMUL_S]] 71 ; CHECK-NEXT: PseudoRET implicit $f10_f 72 %0:fprb(s32) = COPY $f10_f 73 %1:fprb(s32) = COPY $f11_f 74 %2:fprb(s32) = G_FMUL %0, %1 75 $f10_f = COPY %2(s32) 76 PseudoRET implicit $f10_f 77 78... 79--- 80name: fdiv_f32 81legalized: true 82regBankSelected: true 83tracksRegLiveness: true 84body: | 85 bb.0: 86 liveins: $f10_f, $f11_f 87 88 ; CHECK-LABEL: name: fdiv_f32 89 ; CHECK: liveins: $f10_f, $f11_f 90 ; CHECK-NEXT: {{ $}} 91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 92 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 93 ; CHECK-NEXT: [[FDIV_S:%[0-9]+]]:fpr32 = nofpexcept FDIV_S [[COPY]], [[COPY1]], 7 94 ; CHECK-NEXT: $f10_f = COPY [[FDIV_S]] 95 ; CHECK-NEXT: PseudoRET implicit $f10_f 96 %0:fprb(s32) = COPY $f10_f 97 %1:fprb(s32) = COPY $f11_f 98 %2:fprb(s32) = G_FDIV %0, %1 99 $f10_f = COPY %2(s32) 100 PseudoRET implicit $f10_f 101 102... 103--- 104name: fma_f32 105legalized: true 106regBankSelected: true 107tracksRegLiveness: true 108body: | 109 bb.0: 110 liveins: $f10_f, $f11_f, $f12_f 111 112 ; CHECK-LABEL: name: fma_f32 113 ; CHECK: liveins: $f10_f, $f11_f, $f12_f 114 ; CHECK-NEXT: {{ $}} 115 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 116 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 117 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f12_f 118 ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nofpexcept FMADD_S [[COPY]], [[COPY1]], [[COPY2]], 7 119 ; CHECK-NEXT: $f10_f = COPY [[FMADD_S]] 120 ; CHECK-NEXT: PseudoRET implicit $f10_f 121 %0:fprb(s32) = COPY $f10_f 122 %1:fprb(s32) = COPY $f11_f 123 %2:fprb(s32) = COPY $f12_f 124 %3:fprb(s32) = G_FMA %0, %1, %2 125 $f10_f = COPY %3(s32) 126 PseudoRET implicit $f10_f 127 128... 129--- 130name: fneg_f32 131legalized: true 132regBankSelected: true 133tracksRegLiveness: true 134body: | 135 bb.0: 136 liveins: $f10_f, $f11_f, $f12_f 137 138 ; CHECK-LABEL: name: fneg_f32 139 ; CHECK: liveins: $f10_f, $f11_f, $f12_f 140 ; CHECK-NEXT: {{ $}} 141 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 142 ; CHECK-NEXT: [[FSGNJN_S:%[0-9]+]]:fpr32 = FSGNJN_S [[COPY]], [[COPY]] 143 ; CHECK-NEXT: $f10_f = COPY [[FSGNJN_S]] 144 ; CHECK-NEXT: PseudoRET implicit $f10_f 145 %0:fprb(s32) = COPY $f10_f 146 %1:fprb(s32) = G_FNEG %0 147 $f10_f = COPY %1(s32) 148 PseudoRET implicit $f10_f 149 150... 151--- 152name: fabs_f32 153legalized: true 154regBankSelected: true 155tracksRegLiveness: true 156body: | 157 bb.0: 158 liveins: $f10_f, $f11_f, $f12_f 159 160 ; CHECK-LABEL: name: fabs_f32 161 ; CHECK: liveins: $f10_f, $f11_f, $f12_f 162 ; CHECK-NEXT: {{ $}} 163 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 164 ; CHECK-NEXT: [[FSGNJX_S:%[0-9]+]]:fpr32 = FSGNJX_S [[COPY]], [[COPY]] 165 ; CHECK-NEXT: $f10_f = COPY [[FSGNJX_S]] 166 ; CHECK-NEXT: PseudoRET implicit $f10_f 167 %0:fprb(s32) = COPY $f10_f 168 %1:fprb(s32) = G_FABS %0 169 $f10_f = COPY %1(s32) 170 PseudoRET implicit $f10_f 171 172... 173--- 174name: fsqrt_f32 175legalized: true 176regBankSelected: true 177tracksRegLiveness: true 178body: | 179 bb.0: 180 liveins: $f10_f, $f11_f, $f12_f 181 182 ; CHECK-LABEL: name: fsqrt_f32 183 ; CHECK: liveins: $f10_f, $f11_f, $f12_f 184 ; CHECK-NEXT: {{ $}} 185 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 186 ; CHECK-NEXT: [[FSQRT_S:%[0-9]+]]:fpr32 = nofpexcept FSQRT_S [[COPY]], 7 187 ; CHECK-NEXT: $f10_f = COPY [[FSQRT_S]] 188 ; CHECK-NEXT: PseudoRET implicit $f10_f 189 %0:fprb(s32) = COPY $f10_f 190 %1:fprb(s32) = G_FSQRT %0 191 $f10_f = COPY %1(s32) 192 PseudoRET implicit $f10_f 193 194... 195--- 196name: fmaxnum_f32 197legalized: true 198regBankSelected: true 199tracksRegLiveness: true 200body: | 201 bb.0: 202 liveins: $f10_f, $f11_f 203 204 ; CHECK-LABEL: name: fmaxnum_f32 205 ; CHECK: liveins: $f10_f, $f11_f 206 ; CHECK-NEXT: {{ $}} 207 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 208 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 209 ; CHECK-NEXT: [[FMAX_S:%[0-9]+]]:fpr32 = nofpexcept FMAX_S [[COPY]], [[COPY1]] 210 ; CHECK-NEXT: $f10_f = COPY [[FMAX_S]] 211 ; CHECK-NEXT: PseudoRET implicit $f10_f 212 %0:fprb(s32) = COPY $f10_f 213 %1:fprb(s32) = COPY $f11_f 214 %2:fprb(s32) = G_FMAXNUM %0, %1 215 $f10_f = COPY %2(s32) 216 PseudoRET implicit $f10_f 217 218... 219--- 220name: fminnum_f32 221legalized: true 222regBankSelected: true 223tracksRegLiveness: true 224body: | 225 bb.0: 226 liveins: $f10_f, $f11_f 227 228 ; CHECK-LABEL: name: fminnum_f32 229 ; CHECK: liveins: $f10_f, $f11_f 230 ; CHECK-NEXT: {{ $}} 231 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 232 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 233 ; CHECK-NEXT: [[FMIN_S:%[0-9]+]]:fpr32 = nofpexcept FMIN_S [[COPY]], [[COPY1]] 234 ; CHECK-NEXT: $f10_f = COPY [[FMIN_S]] 235 ; CHECK-NEXT: PseudoRET implicit $f10_f 236 %0:fprb(s32) = COPY $f10_f 237 %1:fprb(s32) = COPY $f11_f 238 %2:fprb(s32) = G_FMINNUM %0, %1 239 $f10_f = COPY %2(s32) 240 PseudoRET implicit $f10_f 241 242... 243--- 244name: fcopysign_f32_f32 245legalized: true 246regBankSelected: true 247tracksRegLiveness: true 248body: | 249 bb.0: 250 liveins: $f10_f, $f11_f 251 252 ; CHECK-LABEL: name: fcopysign_f32_f32 253 ; CHECK: liveins: $f10_f, $f11_f 254 ; CHECK-NEXT: {{ $}} 255 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 256 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 257 ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[COPY1]] 258 ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]] 259 ; CHECK-NEXT: PseudoRET implicit $f10_f 260 %0:fprb(s32) = COPY $f10_f 261 %1:fprb(s32) = COPY $f11_f 262 %2:fprb(s32) = G_FCOPYSIGN %0, %1 263 $f10_f = COPY %2(s32) 264 PseudoRET implicit $f10_f 265 266... 267--- 268name: fcopysign_f32_f64 269legalized: true 270regBankSelected: true 271tracksRegLiveness: true 272body: | 273 bb.0: 274 liveins: $f10_f, $f11_d 275 276 ; CHECK-LABEL: name: fcopysign_f32_f64 277 ; CHECK: liveins: $f10_f, $f11_d 278 ; CHECK-NEXT: {{ $}} 279 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 280 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 281 ; CHECK-NEXT: [[FCVT_S_D:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_D [[COPY1]], 7 282 ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_D]] 283 ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]] 284 ; CHECK-NEXT: PseudoRET implicit $f10_f 285 %0:fprb(s32) = COPY $f10_f 286 %1:fprb(s64) = COPY $f11_d 287 %2:fprb(s32) = G_FCOPYSIGN %0, %1 288 $f10_f = COPY %2(s32) 289 PseudoRET implicit $f10_f 290 291... 292--- 293name: fadd_f64 294legalized: true 295regBankSelected: true 296tracksRegLiveness: true 297body: | 298 bb.0: 299 liveins: $f10_d, $f11_d 300 301 ; CHECK-LABEL: name: fadd_f64 302 ; CHECK: liveins: $f10_d, $f11_d 303 ; CHECK-NEXT: {{ $}} 304 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 305 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 306 ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7 307 ; CHECK-NEXT: $f10_d = COPY [[FADD_D]] 308 ; CHECK-NEXT: PseudoRET implicit $f10_d 309 %0:fprb(s64) = COPY $f10_d 310 %1:fprb(s64) = COPY $f11_d 311 %2:fprb(s64) = G_FADD %0, %1 312 $f10_d = COPY %2(s64) 313 PseudoRET implicit $f10_d 314 315... 316--- 317name: fsub_f64 318legalized: true 319regBankSelected: true 320tracksRegLiveness: true 321body: | 322 bb.0: 323 liveins: $f10_d, $f11_d 324 325 ; CHECK-LABEL: name: fsub_f64 326 ; CHECK: liveins: $f10_d, $f11_d 327 ; CHECK-NEXT: {{ $}} 328 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 329 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 330 ; CHECK-NEXT: [[FSUB_D:%[0-9]+]]:fpr64 = nofpexcept FSUB_D [[COPY]], [[COPY1]], 7 331 ; CHECK-NEXT: $f10_d = COPY [[FSUB_D]] 332 ; CHECK-NEXT: PseudoRET implicit $f10_d 333 %0:fprb(s64) = COPY $f10_d 334 %1:fprb(s64) = COPY $f11_d 335 %2:fprb(s64) = G_FSUB %0, %1 336 $f10_d = COPY %2(s64) 337 PseudoRET implicit $f10_d 338 339... 340--- 341name: fmul_f64 342legalized: true 343regBankSelected: true 344tracksRegLiveness: true 345body: | 346 bb.0: 347 liveins: $f10_d, $f11_d 348 349 ; CHECK-LABEL: name: fmul_f64 350 ; CHECK: liveins: $f10_d, $f11_d 351 ; CHECK-NEXT: {{ $}} 352 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 353 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 354 ; CHECK-NEXT: [[FMUL_D:%[0-9]+]]:fpr64 = nofpexcept FMUL_D [[COPY]], [[COPY1]], 7 355 ; CHECK-NEXT: $f10_d = COPY [[FMUL_D]] 356 ; CHECK-NEXT: PseudoRET implicit $f10_d 357 %0:fprb(s64) = COPY $f10_d 358 %1:fprb(s64) = COPY $f11_d 359 %2:fprb(s64) = G_FMUL %0, %1 360 $f10_d = COPY %2(s64) 361 PseudoRET implicit $f10_d 362 363... 364--- 365name: fdiv_f64 366legalized: true 367regBankSelected: true 368tracksRegLiveness: true 369body: | 370 bb.0: 371 liveins: $f10_d, $f11_d 372 373 ; CHECK-LABEL: name: fdiv_f64 374 ; CHECK: liveins: $f10_d, $f11_d 375 ; CHECK-NEXT: {{ $}} 376 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 377 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 378 ; CHECK-NEXT: [[FDIV_D:%[0-9]+]]:fpr64 = nofpexcept FDIV_D [[COPY]], [[COPY1]], 7 379 ; CHECK-NEXT: $f10_d = COPY [[FDIV_D]] 380 ; CHECK-NEXT: PseudoRET implicit $f10_d 381 %0:fprb(s64) = COPY $f10_d 382 %1:fprb(s64) = COPY $f11_d 383 %2:fprb(s64) = G_FDIV %0, %1 384 $f10_d = COPY %2(s64) 385 PseudoRET implicit $f10_d 386 387... 388--- 389name: fma_f64 390legalized: true 391regBankSelected: true 392tracksRegLiveness: true 393body: | 394 bb.0: 395 liveins: $f10_d, $f11_d, $f12_d 396 397 ; CHECK-LABEL: name: fma_f64 398 ; CHECK: liveins: $f10_d, $f11_d, $f12_d 399 ; CHECK-NEXT: {{ $}} 400 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 401 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 402 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f12_d 403 ; CHECK-NEXT: [[FMADD_D:%[0-9]+]]:fpr64 = nofpexcept FMADD_D [[COPY]], [[COPY1]], [[COPY2]], 7 404 ; CHECK-NEXT: $f10_d = COPY [[FMADD_D]] 405 ; CHECK-NEXT: PseudoRET implicit $f10_d 406 %0:fprb(s64) = COPY $f10_d 407 %1:fprb(s64) = COPY $f11_d 408 %2:fprb(s64) = COPY $f12_d 409 %3:fprb(s64) = G_FMA %0, %1, %2 410 $f10_d = COPY %3(s64) 411 PseudoRET implicit $f10_d 412 413... 414--- 415name: fneg_f64 416legalized: true 417regBankSelected: true 418tracksRegLiveness: true 419body: | 420 bb.0: 421 liveins: $f10_d 422 423 ; CHECK-LABEL: name: fneg_f64 424 ; CHECK: liveins: $f10_d 425 ; CHECK-NEXT: {{ $}} 426 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 427 ; CHECK-NEXT: [[FSGNJN_D:%[0-9]+]]:fpr64 = FSGNJN_D [[COPY]], [[COPY]] 428 ; CHECK-NEXT: $f10_d = COPY [[FSGNJN_D]] 429 ; CHECK-NEXT: PseudoRET implicit $f10_d 430 %0:fprb(s64) = COPY $f10_d 431 %1:fprb(s64) = G_FNEG %0 432 $f10_d = COPY %1(s64) 433 PseudoRET implicit $f10_d 434 435... 436--- 437name: fabs_f64 438legalized: true 439regBankSelected: true 440tracksRegLiveness: true 441body: | 442 bb.0: 443 liveins: $f10_d 444 445 ; CHECK-LABEL: name: fabs_f64 446 ; CHECK: liveins: $f10_d 447 ; CHECK-NEXT: {{ $}} 448 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 449 ; CHECK-NEXT: [[FSGNJX_D:%[0-9]+]]:fpr64 = FSGNJX_D [[COPY]], [[COPY]] 450 ; CHECK-NEXT: $f10_d = COPY [[FSGNJX_D]] 451 ; CHECK-NEXT: PseudoRET implicit $f10_d 452 %0:fprb(s64) = COPY $f10_d 453 %1:fprb(s64) = G_FABS %0 454 $f10_d = COPY %1(s64) 455 PseudoRET implicit $f10_d 456 457... 458--- 459name: fsqrt_f64 460legalized: true 461regBankSelected: true 462tracksRegLiveness: true 463body: | 464 bb.0: 465 liveins: $f10_d 466 467 ; CHECK-LABEL: name: fsqrt_f64 468 ; CHECK: liveins: $f10_d 469 ; CHECK-NEXT: {{ $}} 470 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 471 ; CHECK-NEXT: [[FSQRT_D:%[0-9]+]]:fpr64 = nofpexcept FSQRT_D [[COPY]], 7 472 ; CHECK-NEXT: $f10_d = COPY [[FSQRT_D]] 473 ; CHECK-NEXT: PseudoRET implicit $f10_d 474 %0:fprb(s64) = COPY $f10_d 475 %1:fprb(s64) = G_FSQRT %0 476 $f10_d = COPY %1(s64) 477 PseudoRET implicit $f10_d 478 479... 480--- 481name: fmaxnum_f64 482legalized: true 483regBankSelected: true 484tracksRegLiveness: true 485body: | 486 bb.0: 487 liveins: $f10_d, $f11_d 488 489 ; CHECK-LABEL: name: fmaxnum_f64 490 ; CHECK: liveins: $f10_d, $f11_d 491 ; CHECK-NEXT: {{ $}} 492 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 493 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 494 ; CHECK-NEXT: [[FMAX_D:%[0-9]+]]:fpr64 = nofpexcept FMAX_D [[COPY]], [[COPY1]] 495 ; CHECK-NEXT: $f10_d = COPY [[FMAX_D]] 496 ; CHECK-NEXT: PseudoRET implicit $f10_d 497 %0:fprb(s64) = COPY $f10_d 498 %1:fprb(s64) = COPY $f11_d 499 %2:fprb(s64) = G_FMAXNUM %0, %1 500 $f10_d = COPY %2(s64) 501 PseudoRET implicit $f10_d 502 503... 504--- 505name: fminnum_f64 506legalized: true 507regBankSelected: true 508tracksRegLiveness: true 509body: | 510 bb.0: 511 liveins: $f10_d, $f11_d 512 513 ; CHECK-LABEL: name: fminnum_f64 514 ; CHECK: liveins: $f10_d, $f11_d 515 ; CHECK-NEXT: {{ $}} 516 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 517 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 518 ; CHECK-NEXT: [[FMIN_D:%[0-9]+]]:fpr64 = nofpexcept FMIN_D [[COPY]], [[COPY1]] 519 ; CHECK-NEXT: $f10_d = COPY [[FMIN_D]] 520 ; CHECK-NEXT: PseudoRET implicit $f10_d 521 %0:fprb(s64) = COPY $f10_d 522 %1:fprb(s64) = COPY $f11_d 523 %2:fprb(s64) = G_FMINNUM %0, %1 524 $f10_d = COPY %2(s64) 525 PseudoRET implicit $f10_d 526 527... 528--- 529name: fcopysign_f64_f64 530legalized: true 531regBankSelected: true 532tracksRegLiveness: true 533body: | 534 bb.0: 535 liveins: $f10_d, $f11_d 536 537 ; CHECK-LABEL: name: fcopysign_f64_f64 538 ; CHECK: liveins: $f10_d, $f11_d 539 ; CHECK-NEXT: {{ $}} 540 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 541 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d 542 ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[COPY1]] 543 ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]] 544 ; CHECK-NEXT: PseudoRET implicit $f10_d 545 %0:fprb(s64) = COPY $f10_d 546 %1:fprb(s64) = COPY $f11_d 547 %2:fprb(s64) = G_FCOPYSIGN %0, %1 548 $f10_d = COPY %2(s64) 549 PseudoRET implicit $f10_d 550 551... 552--- 553name: fcopysign_f64_f32 554legalized: true 555regBankSelected: true 556tracksRegLiveness: true 557body: | 558 bb.0: 559 liveins: $f10_d, $f11_f 560 561 ; CHECK-LABEL: name: fcopysign_f64_f32 562 ; CHECK: liveins: $f10_d, $f11_f 563 ; CHECK-NEXT: {{ $}} 564 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d 565 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 566 ; CHECK-NEXT: [[FCVT_D_S:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_S [[COPY1]], 0 567 ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_S]] 568 ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]] 569 ; CHECK-NEXT: PseudoRET implicit $f10_d 570 %0:fprb(s64) = COPY $f10_d 571 %1:fprb(s32) = COPY $f11_f 572 %2:fprb(s64) = G_FCOPYSIGN %0, %1 573 $f10_d = COPY %2(s64) 574 PseudoRET implicit $f10_d 575 576... 577