xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv32.mir (revision 5bb03d25f7a0d713ba16a60bd6bf7e611a2ac96c) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
3# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
4# RUN:   | FileCheck -check-prefix=RV32I %s
5
6---
7name:            ctpop_s32
8legalized:       true
9regBankSelected: true
10body:             |
11  bb.0.entry:
12    ; RV32I-LABEL: name: ctpop_s32
13    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14    ; RV32I-NEXT: [[CPOP:%[0-9]+]]:gpr = CPOP [[COPY]]
15    ; RV32I-NEXT: $x10 = COPY [[CPOP]]
16    ; RV32I-NEXT: PseudoRET implicit $x10
17    %0:gprb(s32) = COPY $x10
18    %1:gprb(s32) = G_CTPOP %0
19    $x10 = COPY %1(s32)
20    PseudoRET implicit $x10
21
22...
23