1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ 3# RUN: | FileCheck -check-prefix=RV32I %s 4 5--- 6name: virt_to_phys 7legalized: true 8regBankSelected: true 9tracksRegLiveness: true 10body: | 11 bb.0.entry: 12 13 ; RV32I-LABEL: name: virt_to_phys 14 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 15 ; RV32I-NEXT: $x10 = COPY [[ADDI]] 16 ; RV32I-NEXT: PseudoRET implicit $x10 17 %0:gprb(s32) = G_CONSTANT i32 1 18 $x10 = COPY %0(s32) 19 PseudoRET implicit $x10 20 21... 22--- 23name: phys_to_phys 24legalized: true 25regBankSelected: true 26tracksRegLiveness: true 27body: | 28 bb.0.entry: 29 liveins: $x10, $x11 30 31 ; RV32I-LABEL: name: phys_to_phys 32 ; RV32I: liveins: $x10, $x11 33 ; RV32I-NEXT: {{ $}} 34 ; RV32I-NEXT: $x10 = COPY $x11 35 ; RV32I-NEXT: PseudoRET implicit $x10 36 $x10 = COPY $x11 37 PseudoRET implicit $x10 38 39... 40--- 41name: virt_to_virt 42legalized: true 43regBankSelected: true 44tracksRegLiveness: true 45body: | 46 bb.0.entry: 47 48 ; RV32I-LABEL: name: virt_to_virt 49 ; RV32I: PseudoRET 50 %0:gprb(s32) = G_CONSTANT i32 1 51 %1:gprb(s32) = COPY %0(s32) 52 PseudoRET 53 54... 55--- 56name: phys_to_virt 57legalized: true 58regBankSelected: true 59tracksRegLiveness: true 60body: | 61 bb.0.entry: 62 liveins: $x10 63 64 ; RV32I-LABEL: name: phys_to_virt 65 ; RV32I: liveins: $x10 66 ; RV32I-NEXT: {{ $}} 67 ; RV32I-NEXT: PseudoRET 68 %0:gprb(s32) = COPY $x10 69 PseudoRET 70 71... 72