xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir (revision ba3ef331b4568b5996172076572581e68c2d3c0c) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
3# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
5# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
6
7---
8name:            bswap_s32
9legalized:       true
10regBankSelected: true
11body:             |
12  bb.0.entry:
13    ; CHECK-LABEL: name: bswap_s32
14    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
15    ; CHECK-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
16    ; CHECK-NEXT: $x10 = COPY [[REV8_RV32_]]
17    ; CHECK-NEXT: PseudoRET implicit $x10
18    %0:gprb(s32) = COPY $x10
19    %1:gprb(s32) = G_BSWAP %0
20    $x10 = COPY %1(s32)
21    PseudoRET implicit $x10
22
23...
24