xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir (revision 179a2e04439d449bbcd7482070c27983ef345c20)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
3# RUN:   -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
4
5---
6name:            indirectbr
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  ; RV32I-LABEL: name: indirectbr
12  ; RV32I: bb.0:
13  ; RV32I-NEXT:   successors: %bb.1, %bb.2
14  ; RV32I-NEXT:   liveins: $x10
15  ; RV32I-NEXT: {{  $}}
16  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gprjalr = COPY $x10
17  ; RV32I-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
18  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x0
19  ; RV32I-NEXT:   PseudoBRIND [[COPY]], 0
20  ; RV32I-NEXT: {{  $}}
21  ; RV32I-NEXT: bb.1:
22  ; RV32I-NEXT:   $x10 = COPY [[COPY1]]
23  ; RV32I-NEXT:   PseudoRET implicit $x10
24  ; RV32I-NEXT: {{  $}}
25  ; RV32I-NEXT: bb.2:
26  ; RV32I-NEXT:   $x10 = COPY [[ADDI]]
27  ; RV32I-NEXT:   PseudoRET implicit $x10
28  bb.1:
29    successors: %bb.2, %bb.3
30    liveins: $x10
31
32    %0:gprb(p0) = COPY $x10
33    %1:gprb(s32) = G_CONSTANT i32 1
34    %2:gprb(s32) = G_CONSTANT i32 0
35    G_BRINDIRECT %0(p0)
36
37  bb.2:
38    $x10 = COPY %2(s32)
39    PseudoRET implicit $x10
40
41  bb.3:
42    $x10 = COPY %1(s32)
43    PseudoRET implicit $x10
44
45...
46