1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ 3# RUN: | FileCheck -check-prefix=RV32I %s 4 5--- 6name: brcond 7legalized: true 8regBankSelected: true 9tracksRegLiveness: true 10body: | 11 ; RV32I-LABEL: name: brcond 12 ; RV32I: bb.0: 13 ; RV32I-NEXT: liveins: $x10, $x11, $x12 14 ; RV32I-NEXT: {{ $}} 15 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 16 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 17 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 18 ; RV32I-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 19 ; RV32I-NEXT: BEQ [[LW]], [[COPY]], %bb.14 20 ; RV32I-NEXT: PseudoBR %bb.1 21 ; RV32I-NEXT: {{ $}} 22 ; RV32I-NEXT: bb.1: 23 ; RV32I-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 24 ; RV32I-NEXT: BNE [[LW1]], [[COPY]], %bb.14 25 ; RV32I-NEXT: PseudoBR %bb.2 26 ; RV32I-NEXT: {{ $}} 27 ; RV32I-NEXT: bb.2: 28 ; RV32I-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 29 ; RV32I-NEXT: BLT [[LW2]], [[COPY]], %bb.14 30 ; RV32I-NEXT: PseudoBR %bb.3 31 ; RV32I-NEXT: {{ $}} 32 ; RV32I-NEXT: bb.3: 33 ; RV32I-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 34 ; RV32I-NEXT: BGE [[LW3]], [[COPY]], %bb.14 35 ; RV32I-NEXT: PseudoBR %bb.4 36 ; RV32I-NEXT: {{ $}} 37 ; RV32I-NEXT: bb.4: 38 ; RV32I-NEXT: [[LW4:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 39 ; RV32I-NEXT: BLTU [[LW4]], [[COPY]], %bb.14 40 ; RV32I-NEXT: PseudoBR %bb.5 41 ; RV32I-NEXT: {{ $}} 42 ; RV32I-NEXT: bb.5: 43 ; RV32I-NEXT: [[LW5:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 44 ; RV32I-NEXT: BGEU [[LW5]], [[COPY]], %bb.14 45 ; RV32I-NEXT: PseudoBR %bb.6 46 ; RV32I-NEXT: {{ $}} 47 ; RV32I-NEXT: bb.6: 48 ; RV32I-NEXT: [[LW6:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 49 ; RV32I-NEXT: BLT [[COPY]], [[LW6]], %bb.14 50 ; RV32I-NEXT: PseudoBR %bb.7 51 ; RV32I-NEXT: {{ $}} 52 ; RV32I-NEXT: bb.7: 53 ; RV32I-NEXT: [[LW7:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 54 ; RV32I-NEXT: BGE [[COPY]], [[LW7]], %bb.14 55 ; RV32I-NEXT: PseudoBR %bb.8 56 ; RV32I-NEXT: {{ $}} 57 ; RV32I-NEXT: bb.8: 58 ; RV32I-NEXT: [[LW8:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 59 ; RV32I-NEXT: BLTU [[COPY]], [[LW8]], %bb.14 60 ; RV32I-NEXT: PseudoBR %bb.9 61 ; RV32I-NEXT: {{ $}} 62 ; RV32I-NEXT: bb.9: 63 ; RV32I-NEXT: [[LW9:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 64 ; RV32I-NEXT: BGEU [[COPY]], [[LW9]], %bb.14 65 ; RV32I-NEXT: PseudoBR %bb.10 66 ; RV32I-NEXT: {{ $}} 67 ; RV32I-NEXT: bb.10: 68 ; RV32I-NEXT: [[LW10:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 69 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1 70 ; RV32I-NEXT: BNE [[ANDI]], $x0, %bb.14 71 ; RV32I-NEXT: PseudoBR %bb.11 72 ; RV32I-NEXT: {{ $}} 73 ; RV32I-NEXT: bb.11: 74 ; RV32I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000) 75 ; RV32I-NEXT: {{ $}} 76 ; RV32I-NEXT: [[LW11:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 77 ; RV32I-NEXT: BGE [[LW11]], $x0, %bb.14 78 ; RV32I-NEXT: PseudoBR %bb.12 79 ; RV32I-NEXT: {{ $}} 80 ; RV32I-NEXT: bb.12: 81 ; RV32I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000) 82 ; RV32I-NEXT: {{ $}} 83 ; RV32I-NEXT: [[LW12:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 84 ; RV32I-NEXT: BGE $x0, [[LW12]], %bb.14 85 ; RV32I-NEXT: PseudoBR %bb.13 86 ; RV32I-NEXT: {{ $}} 87 ; RV32I-NEXT: bb.13: 88 ; RV32I-NEXT: [[LW13:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) 89 ; RV32I-NEXT: {{ $}} 90 ; RV32I-NEXT: bb.14: 91 ; RV32I-NEXT: PseudoRET 92 bb.1: 93 liveins: $x10, $x11, $x12 94 95 %0:gprb(s32) = COPY $x10 96 %1:gprb(p0) = COPY $x11 97 %3:gprb(s32) = COPY $x12 98 %26:gprb(s32) = G_CONSTANT i32 -1 99 %29:gprb(s32) = G_CONSTANT i32 1 100 %4:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 101 %56:gprb(s32) = G_ICMP intpred(eq), %4(s32), %0 102 G_BRCOND %56(s32), %bb.15 103 G_BR %bb.2 104 105 bb.2: 106 %6:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 107 %54:gprb(s32) = G_ICMP intpred(ne), %6(s32), %0 108 G_BRCOND %54(s32), %bb.15 109 G_BR %bb.3 110 111 bb.3: 112 %8:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 113 %52:gprb(s32) = G_ICMP intpred(slt), %8(s32), %0 114 G_BRCOND %52(s32), %bb.15 115 G_BR %bb.4 116 117 bb.4: 118 %10:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 119 %50:gprb(s32) = G_ICMP intpred(sge), %10(s32), %0 120 G_BRCOND %50(s32), %bb.15 121 G_BR %bb.5 122 123 bb.5: 124 %12:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 125 %48:gprb(s32) = G_ICMP intpred(ult), %12(s32), %0 126 G_BRCOND %48(s32), %bb.15 127 G_BR %bb.6 128 129 bb.6: 130 %14:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 131 %46:gprb(s32) = G_ICMP intpred(uge), %14(s32), %0 132 G_BRCOND %46(s32), %bb.15 133 G_BR %bb.7 134 135 bb.7: 136 %16:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 137 %44:gprb(s32) = G_ICMP intpred(sgt), %16(s32), %0 138 G_BRCOND %44(s32), %bb.15 139 G_BR %bb.8 140 141 bb.8: 142 %18:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 143 %42:gprb(s32) = G_ICMP intpred(sle), %18(s32), %0 144 G_BRCOND %42(s32), %bb.15 145 G_BR %bb.9 146 147 bb.9: 148 %20:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 149 %40:gprb(s32) = G_ICMP intpred(ugt), %20(s32), %0 150 G_BRCOND %40(s32), %bb.15 151 G_BR %bb.10 152 153 bb.10: 154 %22:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 155 %38:gprb(s32) = G_ICMP intpred(ule), %22(s32), %0 156 G_BRCOND %38(s32), %bb.15 157 G_BR %bb.11 158 159 bb.11: 160 %24:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 161 %57:gprb(s32) = G_CONSTANT i32 1 162 %36:gprb(s32) = G_AND %3, %57 163 G_BRCOND %36(s32), %bb.15 164 G_BR %bb.12 165 166 bb.12: 167 successors: %bb.15(0x50000000), %bb.13(0x30000000) 168 169 %25:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 170 %35:gprb(s32) = G_ICMP intpred(sgt), %25(s32), %26 171 G_BRCOND %35(s32), %bb.15 172 G_BR %bb.13 173 174 bb.13: 175 successors: %bb.15(0x30000000), %bb.14(0x50000000) 176 177 %28:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 178 %33:gprb(s32) = G_ICMP intpred(slt), %28(s32), %29 179 G_BRCOND %33(s32), %bb.15 180 G_BR %bb.14 181 182 bb.14: 183 %31:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) 184 185 bb.15: 186 PseudoRET 187 188... 189