1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ 3# RUN: | FileCheck -check-prefix=RV32I %s 4 5--- 6name: mul_i32 7legalized: true 8regBankSelected: true 9tracksRegLiveness: true 10body: | 11 bb.0.entry: 12 liveins: $x10, $x11 13 14 ; RV32I-LABEL: name: mul_i32 15 ; RV32I: liveins: $x10, $x11 16 ; RV32I-NEXT: {{ $}} 17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 18 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 19 ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]] 20 ; RV32I-NEXT: $x10 = COPY [[MUL]] 21 ; RV32I-NEXT: PseudoRET implicit $x10 22 %0:gprb(s32) = COPY $x10 23 %1:gprb(s32) = COPY $x11 24 %2:gprb(s32) = G_MUL %0, %1 25 $x10 = COPY %2(s32) 26 PseudoRET implicit $x10 27 28... 29--- 30name: sdiv_i32 31legalized: true 32regBankSelected: true 33tracksRegLiveness: true 34body: | 35 bb.0.entry: 36 liveins: $x10, $x11 37 38 ; RV32I-LABEL: name: sdiv_i32 39 ; RV32I: liveins: $x10, $x11 40 ; RV32I-NEXT: {{ $}} 41 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 42 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 43 ; RV32I-NEXT: [[DIV:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]] 44 ; RV32I-NEXT: $x10 = COPY [[DIV]] 45 ; RV32I-NEXT: PseudoRET implicit $x10 46 %0:gprb(s32) = COPY $x10 47 %1:gprb(s32) = COPY $x11 48 %2:gprb(s32) = G_SDIV %0, %1 49 $x10 = COPY %2(s32) 50 PseudoRET implicit $x10 51 52... 53--- 54name: srem_i32 55legalized: true 56regBankSelected: true 57tracksRegLiveness: true 58body: | 59 bb.0.entry: 60 liveins: $x10, $x11 61 62 ; RV32I-LABEL: name: srem_i32 63 ; RV32I: liveins: $x10, $x11 64 ; RV32I-NEXT: {{ $}} 65 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 66 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 67 ; RV32I-NEXT: [[REM:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]] 68 ; RV32I-NEXT: $x10 = COPY [[REM]] 69 ; RV32I-NEXT: PseudoRET implicit $x10 70 %0:gprb(s32) = COPY $x10 71 %1:gprb(s32) = COPY $x11 72 %2:gprb(s32) = G_SREM %0, %1 73 $x10 = COPY %2(s32) 74 PseudoRET implicit $x10 75 76... 77--- 78name: smulh_i32 79legalized: true 80regBankSelected: true 81tracksRegLiveness: true 82body: | 83 bb.0.entry: 84 liveins: $x10, $x11 85 86 ; RV32I-LABEL: name: smulh_i32 87 ; RV32I: liveins: $x10, $x11 88 ; RV32I-NEXT: {{ $}} 89 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 90 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 91 ; RV32I-NEXT: [[MULH:%[0-9]+]]:gpr = MULH [[COPY]], [[COPY1]] 92 ; RV32I-NEXT: $x10 = COPY [[MULH]] 93 ; RV32I-NEXT: PseudoRET implicit $x10 94 %0:gprb(s32) = COPY $x10 95 %1:gprb(s32) = COPY $x11 96 %2:gprb(s32) = G_SMULH %0, %1 97 $x10 = COPY %2(s32) 98 PseudoRET implicit $x10 99 100... 101--- 102name: udiv_i32 103legalized: true 104regBankSelected: true 105tracksRegLiveness: true 106body: | 107 bb.0.entry: 108 liveins: $x10, $x11 109 110 ; RV32I-LABEL: name: udiv_i32 111 ; RV32I: liveins: $x10, $x11 112 ; RV32I-NEXT: {{ $}} 113 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 114 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 115 ; RV32I-NEXT: [[DIVU:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]] 116 ; RV32I-NEXT: $x10 = COPY [[DIVU]] 117 ; RV32I-NEXT: PseudoRET implicit $x10 118 %0:gprb(s32) = COPY $x10 119 %1:gprb(s32) = COPY $x11 120 %2:gprb(s32) = G_UDIV %0, %1 121 $x10 = COPY %2(s32) 122 PseudoRET implicit $x10 123 124... 125--- 126name: urem_i32 127legalized: true 128regBankSelected: true 129tracksRegLiveness: true 130body: | 131 bb.0.entry: 132 liveins: $x10, $x11 133 134 ; RV32I-LABEL: name: urem_i32 135 ; RV32I: liveins: $x10, $x11 136 ; RV32I-NEXT: {{ $}} 137 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 138 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 139 ; RV32I-NEXT: [[REMU:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]] 140 ; RV32I-NEXT: $x10 = COPY [[REMU]] 141 ; RV32I-NEXT: PseudoRET implicit $x10 142 %0:gprb(s32) = COPY $x10 143 %1:gprb(s32) = COPY $x11 144 %2:gprb(s32) = G_UREM %0, %1 145 $x10 = COPY %2(s32) 146 PseudoRET implicit $x10 147 148... 149--- 150name: mul_i64 151legalized: true 152regBankSelected: true 153tracksRegLiveness: true 154body: | 155 bb.0.entry: 156 liveins: $x10, $x11, $x12, $x13 157 158 ; RV32I-LABEL: name: mul_i64 159 ; RV32I: liveins: $x10, $x11, $x12, $x13 160 ; RV32I-NEXT: {{ $}} 161 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 162 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 163 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 164 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 165 ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY2]] 166 ; RV32I-NEXT: [[MUL1:%[0-9]+]]:gpr = MUL [[COPY1]], [[COPY2]] 167 ; RV32I-NEXT: [[MUL2:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY3]] 168 ; RV32I-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[COPY2]] 169 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[MUL1]], [[MUL2]] 170 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[MULHU]] 171 ; RV32I-NEXT: $x10 = COPY [[MUL]] 172 ; RV32I-NEXT: $x11 = COPY [[ADD1]] 173 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 174 %0:gprb(s32) = COPY $x10 175 %1:gprb(s32) = COPY $x11 176 %2:gprb(s32) = COPY $x12 177 %3:gprb(s32) = COPY $x13 178 %4:gprb(s32) = G_MUL %0, %2 179 %5:gprb(s32) = G_MUL %1, %2 180 %6:gprb(s32) = G_MUL %0, %3 181 %7:gprb(s32) = G_UMULH %0, %2 182 %8:gprb(s32) = G_ADD %5, %6 183 %9:gprb(s32) = G_ADD %8, %7 184 $x10 = COPY %4(s32) 185 $x11 = COPY %9(s32) 186 PseudoRET implicit $x10, implicit $x11 187 188... 189