xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/fpr-gpr-copy-rv64.ll (revision 77e88db6b7cd982769a852b0fedfc57b3374d1d9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -target-abi=lp64 \
3; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s
4
5; Test copying between FPR64 and GPR on RV64.
6; FIXME: This test should be replaced with a more general calling convention
7; test once we have more FP implemented.
8
9define double @fadd_f64(double %x, double %y) {
10; RV64I-LABEL: fadd_f64:
11; RV64I:       # %bb.0:
12; RV64I-NEXT:    fmv.d.x fa5, a0
13; RV64I-NEXT:    fmv.d.x fa4, a1
14; RV64I-NEXT:    fadd.d fa5, fa5, fa4
15; RV64I-NEXT:    fmv.x.d a0, fa5
16; RV64I-NEXT:    ret
17  %a = fadd double %x, %y
18  ret double %a
19}
20
21; Test copying between FPR32 and GPR on RV64.
22; FIXME: This test should be replaced with a more general calling convention
23; test once we have more FP implemented.
24
25define float @fadd_f32(float %x, float %y) {
26; RV32I-LABEL: fadd:
27; RV32I:       # %bb.0:
28; RV32I-NEXT:    fmv.d.x fa5, a0
29; RV32I-NEXT:    fmv.d.x fa4, a1
30; RV32I-NEXT:    fadd.d fa5, fa5, fa4
31; RV32I-NEXT:    fmv.x.d a0, fa5
32; RV32I-NEXT:    ret
33  %a = fadd float %x, %y
34  ret float %a
35}
36