xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll (revision 115872902b9b056d42e24273f93a2be7c93d2f54) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -global-isel -mattr=+f -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s
4; RUN: llc -mtriple=riscv64 -global-isel -mattr=+f -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
6; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV32I %s
8; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64I %s
10
11define i32 @fcmp_false(float %a, float %b) nounwind {
12; CHECKIF-LABEL: fcmp_false:
13; CHECKIF:       # %bb.0:
14; CHECKIF-NEXT:    li a0, 0
15; CHECKIF-NEXT:    ret
16;
17; RV32I-LABEL: fcmp_false:
18; RV32I:       # %bb.0:
19; RV32I-NEXT:    li a0, 0
20; RV32I-NEXT:    ret
21;
22; RV64I-LABEL: fcmp_false:
23; RV64I:       # %bb.0:
24; RV64I-NEXT:    li a0, 0
25; RV64I-NEXT:    ret
26  %1 = fcmp false float %a, %b
27  %2 = zext i1 %1 to i32
28  ret i32 %2
29}
30
31; FIXME: slli+srli on RV64 are unnecessary
32define i32 @fcmp_oeq(float %a, float %b) nounwind {
33; CHECKIF-LABEL: fcmp_oeq:
34; CHECKIF:       # %bb.0:
35; CHECKIF-NEXT:    feq.s a0, fa0, fa1
36; CHECKIF-NEXT:    ret
37;
38; RV32I-LABEL: fcmp_oeq:
39; RV32I:       # %bb.0:
40; RV32I-NEXT:    addi sp, sp, -16
41; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
42; RV32I-NEXT:    call __eqsf2
43; RV32I-NEXT:    seqz a0, a0
44; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
45; RV32I-NEXT:    addi sp, sp, 16
46; RV32I-NEXT:    ret
47;
48; RV64I-LABEL: fcmp_oeq:
49; RV64I:       # %bb.0:
50; RV64I-NEXT:    addi sp, sp, -16
51; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
52; RV64I-NEXT:    call __eqsf2
53; RV64I-NEXT:    sext.w a0, a0
54; RV64I-NEXT:    seqz a0, a0
55; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
56; RV64I-NEXT:    addi sp, sp, 16
57; RV64I-NEXT:    ret
58  %1 = fcmp oeq float %a, %b
59  %2 = zext i1 %1 to i32
60  ret i32 %2
61}
62
63; FIXME: sext.w on RV64 is unnecessary
64define i32 @fcmp_ogt(float %a, float %b) nounwind {
65; CHECKIF-LABEL: fcmp_ogt:
66; CHECKIF:       # %bb.0:
67; CHECKIF-NEXT:    flt.s a0, fa1, fa0
68; CHECKIF-NEXT:    ret
69;
70; RV32I-LABEL: fcmp_ogt:
71; RV32I:       # %bb.0:
72; RV32I-NEXT:    addi sp, sp, -16
73; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
74; RV32I-NEXT:    call __gtsf2
75; RV32I-NEXT:    sgtz a0, a0
76; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
77; RV32I-NEXT:    addi sp, sp, 16
78; RV32I-NEXT:    ret
79;
80; RV64I-LABEL: fcmp_ogt:
81; RV64I:       # %bb.0:
82; RV64I-NEXT:    addi sp, sp, -16
83; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
84; RV64I-NEXT:    call __gtsf2
85; RV64I-NEXT:    sext.w a0, a0
86; RV64I-NEXT:    sgtz a0, a0
87; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
88; RV64I-NEXT:    addi sp, sp, 16
89; RV64I-NEXT:    ret
90  %1 = fcmp ogt float %a, %b
91  %2 = zext i1 %1 to i32
92  ret i32 %2
93}
94
95; FIXME: sext.w on RV64 is unnecessary
96define i32 @fcmp_oge(float %a, float %b) nounwind {
97; CHECKIF-LABEL: fcmp_oge:
98; CHECKIF:       # %bb.0:
99; CHECKIF-NEXT:    fle.s a0, fa1, fa0
100; CHECKIF-NEXT:    ret
101;
102; RV32I-LABEL: fcmp_oge:
103; RV32I:       # %bb.0:
104; RV32I-NEXT:    addi sp, sp, -16
105; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
106; RV32I-NEXT:    call __gesf2
107; RV32I-NEXT:    slti a0, a0, 0
108; RV32I-NEXT:    xori a0, a0, 1
109; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
110; RV32I-NEXT:    addi sp, sp, 16
111; RV32I-NEXT:    ret
112;
113; RV64I-LABEL: fcmp_oge:
114; RV64I:       # %bb.0:
115; RV64I-NEXT:    addi sp, sp, -16
116; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
117; RV64I-NEXT:    call __gesf2
118; RV64I-NEXT:    sext.w a0, a0
119; RV64I-NEXT:    slti a0, a0, 0
120; RV64I-NEXT:    xori a0, a0, 1
121; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
122; RV64I-NEXT:    addi sp, sp, 16
123; RV64I-NEXT:    ret
124  %1 = fcmp oge float %a, %b
125  %2 = zext i1 %1 to i32
126  ret i32 %2
127}
128
129; FIXME: sext.w on RV64 is unnecessary
130define i32 @fcmp_olt(float %a, float %b) nounwind {
131; CHECKIF-LABEL: fcmp_olt:
132; CHECKIF:       # %bb.0:
133; CHECKIF-NEXT:    flt.s a0, fa0, fa1
134; CHECKIF-NEXT:    ret
135;
136; RV32I-LABEL: fcmp_olt:
137; RV32I:       # %bb.0:
138; RV32I-NEXT:    addi sp, sp, -16
139; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
140; RV32I-NEXT:    call __ltsf2
141; RV32I-NEXT:    slti a0, a0, 0
142; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
143; RV32I-NEXT:    addi sp, sp, 16
144; RV32I-NEXT:    ret
145;
146; RV64I-LABEL: fcmp_olt:
147; RV64I:       # %bb.0:
148; RV64I-NEXT:    addi sp, sp, -16
149; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
150; RV64I-NEXT:    call __ltsf2
151; RV64I-NEXT:    sext.w a0, a0
152; RV64I-NEXT:    slti a0, a0, 0
153; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
154; RV64I-NEXT:    addi sp, sp, 16
155; RV64I-NEXT:    ret
156  %1 = fcmp olt float %a, %b
157  %2 = zext i1 %1 to i32
158  ret i32 %2
159}
160
161; FIXME: sext.w on RV64 is unnecessary
162; FIXME: sgtz+xori can be slti a0, a0, 1
163define i32 @fcmp_ole(float %a, float %b) nounwind {
164; CHECKIF-LABEL: fcmp_ole:
165; CHECKIF:       # %bb.0:
166; CHECKIF-NEXT:    fle.s a0, fa0, fa1
167; CHECKIF-NEXT:    ret
168;
169; RV32I-LABEL: fcmp_ole:
170; RV32I:       # %bb.0:
171; RV32I-NEXT:    addi sp, sp, -16
172; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
173; RV32I-NEXT:    call __lesf2
174; RV32I-NEXT:    sgtz a0, a0
175; RV32I-NEXT:    xori a0, a0, 1
176; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
177; RV32I-NEXT:    addi sp, sp, 16
178; RV32I-NEXT:    ret
179;
180; RV64I-LABEL: fcmp_ole:
181; RV64I:       # %bb.0:
182; RV64I-NEXT:    addi sp, sp, -16
183; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
184; RV64I-NEXT:    call __lesf2
185; RV64I-NEXT:    sext.w a0, a0
186; RV64I-NEXT:    sgtz a0, a0
187; RV64I-NEXT:    xori a0, a0, 1
188; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
189; RV64I-NEXT:    addi sp, sp, 16
190; RV64I-NEXT:    ret
191  %1 = fcmp ole float %a, %b
192  %2 = zext i1 %1 to i32
193  ret i32 %2
194}
195
196; FIXME: slli+srli on RV64 are unnecessary
197define i32 @fcmp_one(float %a, float %b) nounwind {
198; CHECKIF-LABEL: fcmp_one:
199; CHECKIF:       # %bb.0:
200; CHECKIF-NEXT:    flt.s a0, fa0, fa1
201; CHECKIF-NEXT:    flt.s a1, fa1, fa0
202; CHECKIF-NEXT:    or a0, a0, a1
203; CHECKIF-NEXT:    ret
204;
205; RV32I-LABEL: fcmp_one:
206; RV32I:       # %bb.0:
207; RV32I-NEXT:    addi sp, sp, -16
208; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
209; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
210; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
211; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
212; RV32I-NEXT:    mv s0, a0
213; RV32I-NEXT:    mv s1, a1
214; RV32I-NEXT:    call __eqsf2
215; RV32I-NEXT:    snez s2, a0
216; RV32I-NEXT:    mv a0, s0
217; RV32I-NEXT:    mv a1, s1
218; RV32I-NEXT:    call __unordsf2
219; RV32I-NEXT:    seqz a0, a0
220; RV32I-NEXT:    and a0, s2, a0
221; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
222; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
223; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
224; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
225; RV32I-NEXT:    addi sp, sp, 16
226; RV32I-NEXT:    ret
227;
228; RV64I-LABEL: fcmp_one:
229; RV64I:       # %bb.0:
230; RV64I-NEXT:    addi sp, sp, -32
231; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
232; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
233; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
234; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
235; RV64I-NEXT:    mv s0, a0
236; RV64I-NEXT:    mv s1, a1
237; RV64I-NEXT:    call __eqsf2
238; RV64I-NEXT:    sext.w a0, a0
239; RV64I-NEXT:    snez s2, a0
240; RV64I-NEXT:    mv a0, s0
241; RV64I-NEXT:    mv a1, s1
242; RV64I-NEXT:    call __unordsf2
243; RV64I-NEXT:    sext.w a0, a0
244; RV64I-NEXT:    seqz a0, a0
245; RV64I-NEXT:    and a0, s2, a0
246; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
247; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
248; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
249; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
250; RV64I-NEXT:    addi sp, sp, 32
251; RV64I-NEXT:    ret
252  %1 = fcmp one float %a, %b
253  %2 = zext i1 %1 to i32
254  ret i32 %2
255}
256
257; FIXME: slli+srli on RV64 are unnecessary
258define i32 @fcmp_ord(float %a, float %b) nounwind {
259; CHECKIF-LABEL: fcmp_ord:
260; CHECKIF:       # %bb.0:
261; CHECKIF-NEXT:    feq.s a0, fa0, fa0
262; CHECKIF-NEXT:    feq.s a1, fa1, fa1
263; CHECKIF-NEXT:    and a0, a0, a1
264; CHECKIF-NEXT:    ret
265;
266; RV32I-LABEL: fcmp_ord:
267; RV32I:       # %bb.0:
268; RV32I-NEXT:    addi sp, sp, -16
269; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
270; RV32I-NEXT:    call __unordsf2
271; RV32I-NEXT:    seqz a0, a0
272; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
273; RV32I-NEXT:    addi sp, sp, 16
274; RV32I-NEXT:    ret
275;
276; RV64I-LABEL: fcmp_ord:
277; RV64I:       # %bb.0:
278; RV64I-NEXT:    addi sp, sp, -16
279; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
280; RV64I-NEXT:    call __unordsf2
281; RV64I-NEXT:    sext.w a0, a0
282; RV64I-NEXT:    seqz a0, a0
283; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
284; RV64I-NEXT:    addi sp, sp, 16
285; RV64I-NEXT:    ret
286  %1 = fcmp ord float %a, %b
287  %2 = zext i1 %1 to i32
288  ret i32 %2
289}
290
291; FIXME: slli+srli on RV64 are unnecessary
292define i32 @fcmp_ueq(float %a, float %b) nounwind {
293; CHECKIF-LABEL: fcmp_ueq:
294; CHECKIF:       # %bb.0:
295; CHECKIF-NEXT:    flt.s a0, fa0, fa1
296; CHECKIF-NEXT:    flt.s a1, fa1, fa0
297; CHECKIF-NEXT:    or a0, a0, a1
298; CHECKIF-NEXT:    xori a0, a0, 1
299; CHECKIF-NEXT:    ret
300;
301; RV32I-LABEL: fcmp_ueq:
302; RV32I:       # %bb.0:
303; RV32I-NEXT:    addi sp, sp, -16
304; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
305; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
306; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
307; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
308; RV32I-NEXT:    mv s0, a0
309; RV32I-NEXT:    mv s1, a1
310; RV32I-NEXT:    call __eqsf2
311; RV32I-NEXT:    seqz s2, a0
312; RV32I-NEXT:    mv a0, s0
313; RV32I-NEXT:    mv a1, s1
314; RV32I-NEXT:    call __unordsf2
315; RV32I-NEXT:    snez a0, a0
316; RV32I-NEXT:    or a0, s2, a0
317; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
318; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
319; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
320; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
321; RV32I-NEXT:    addi sp, sp, 16
322; RV32I-NEXT:    ret
323;
324; RV64I-LABEL: fcmp_ueq:
325; RV64I:       # %bb.0:
326; RV64I-NEXT:    addi sp, sp, -32
327; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
328; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
329; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
330; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
331; RV64I-NEXT:    mv s0, a0
332; RV64I-NEXT:    mv s1, a1
333; RV64I-NEXT:    call __eqsf2
334; RV64I-NEXT:    sext.w a0, a0
335; RV64I-NEXT:    seqz s2, a0
336; RV64I-NEXT:    mv a0, s0
337; RV64I-NEXT:    mv a1, s1
338; RV64I-NEXT:    call __unordsf2
339; RV64I-NEXT:    sext.w a0, a0
340; RV64I-NEXT:    snez a0, a0
341; RV64I-NEXT:    or a0, s2, a0
342; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
343; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
344; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
345; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
346; RV64I-NEXT:    addi sp, sp, 32
347; RV64I-NEXT:    ret
348  %1 = fcmp ueq float %a, %b
349  %2 = zext i1 %1 to i32
350  ret i32 %2
351}
352
353; FIXME: sext.w on RV64 is unnecessary
354define i32 @fcmp_ugt(float %a, float %b) nounwind {
355; CHECKIF-LABEL: fcmp_ugt:
356; CHECKIF:       # %bb.0:
357; CHECKIF-NEXT:    fle.s a0, fa0, fa1
358; CHECKIF-NEXT:    xori a0, a0, 1
359; CHECKIF-NEXT:    ret
360;
361; RV32I-LABEL: fcmp_ugt:
362; RV32I:       # %bb.0:
363; RV32I-NEXT:    addi sp, sp, -16
364; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
365; RV32I-NEXT:    call __lesf2
366; RV32I-NEXT:    sgtz a0, a0
367; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
368; RV32I-NEXT:    addi sp, sp, 16
369; RV32I-NEXT:    ret
370;
371; RV64I-LABEL: fcmp_ugt:
372; RV64I:       # %bb.0:
373; RV64I-NEXT:    addi sp, sp, -16
374; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
375; RV64I-NEXT:    call __lesf2
376; RV64I-NEXT:    sext.w a0, a0
377; RV64I-NEXT:    sgtz a0, a0
378; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
379; RV64I-NEXT:    addi sp, sp, 16
380; RV64I-NEXT:    ret
381  %1 = fcmp ugt float %a, %b
382  %2 = zext i1 %1 to i32
383  ret i32 %2
384}
385
386; FIXME: sext.w on RV64 is unnecessary
387define i32 @fcmp_uge(float %a, float %b) nounwind {
388; CHECKIF-LABEL: fcmp_uge:
389; CHECKIF:       # %bb.0:
390; CHECKIF-NEXT:    flt.s a0, fa0, fa1
391; CHECKIF-NEXT:    xori a0, a0, 1
392; CHECKIF-NEXT:    ret
393;
394; RV32I-LABEL: fcmp_uge:
395; RV32I:       # %bb.0:
396; RV32I-NEXT:    addi sp, sp, -16
397; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
398; RV32I-NEXT:    call __ltsf2
399; RV32I-NEXT:    slti a0, a0, 0
400; RV32I-NEXT:    xori a0, a0, 1
401; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
402; RV32I-NEXT:    addi sp, sp, 16
403; RV32I-NEXT:    ret
404;
405; RV64I-LABEL: fcmp_uge:
406; RV64I:       # %bb.0:
407; RV64I-NEXT:    addi sp, sp, -16
408; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
409; RV64I-NEXT:    call __ltsf2
410; RV64I-NEXT:    sext.w a0, a0
411; RV64I-NEXT:    slti a0, a0, 0
412; RV64I-NEXT:    xori a0, a0, 1
413; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
414; RV64I-NEXT:    addi sp, sp, 16
415; RV64I-NEXT:    ret
416  %1 = fcmp uge float %a, %b
417  %2 = zext i1 %1 to i32
418  ret i32 %2
419}
420
421; FIXME: sext.w on RV64 is unnecessary
422define i32 @fcmp_ult(float %a, float %b) nounwind {
423; CHECKIF-LABEL: fcmp_ult:
424; CHECKIF:       # %bb.0:
425; CHECKIF-NEXT:    fle.s a0, fa1, fa0
426; CHECKIF-NEXT:    xori a0, a0, 1
427; CHECKIF-NEXT:    ret
428;
429; RV32I-LABEL: fcmp_ult:
430; RV32I:       # %bb.0:
431; RV32I-NEXT:    addi sp, sp, -16
432; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
433; RV32I-NEXT:    call __gesf2
434; RV32I-NEXT:    slti a0, a0, 0
435; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
436; RV32I-NEXT:    addi sp, sp, 16
437; RV32I-NEXT:    ret
438;
439; RV64I-LABEL: fcmp_ult:
440; RV64I:       # %bb.0:
441; RV64I-NEXT:    addi sp, sp, -16
442; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
443; RV64I-NEXT:    call __gesf2
444; RV64I-NEXT:    sext.w a0, a0
445; RV64I-NEXT:    slti a0, a0, 0
446; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
447; RV64I-NEXT:    addi sp, sp, 16
448; RV64I-NEXT:    ret
449  %1 = fcmp ult float %a, %b
450  %2 = zext i1 %1 to i32
451  ret i32 %2
452}
453
454; FIXME: sext.w on RV64 is unnecessary
455; FIXME: sgtz+xori can be slti a0, a0, 1
456define i32 @fcmp_ule(float %a, float %b) nounwind {
457; CHECKIF-LABEL: fcmp_ule:
458; CHECKIF:       # %bb.0:
459; CHECKIF-NEXT:    flt.s a0, fa1, fa0
460; CHECKIF-NEXT:    xori a0, a0, 1
461; CHECKIF-NEXT:    ret
462;
463; RV32I-LABEL: fcmp_ule:
464; RV32I:       # %bb.0:
465; RV32I-NEXT:    addi sp, sp, -16
466; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
467; RV32I-NEXT:    call __gtsf2
468; RV32I-NEXT:    sgtz a0, a0
469; RV32I-NEXT:    xori a0, a0, 1
470; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
471; RV32I-NEXT:    addi sp, sp, 16
472; RV32I-NEXT:    ret
473;
474; RV64I-LABEL: fcmp_ule:
475; RV64I:       # %bb.0:
476; RV64I-NEXT:    addi sp, sp, -16
477; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
478; RV64I-NEXT:    call __gtsf2
479; RV64I-NEXT:    sext.w a0, a0
480; RV64I-NEXT:    sgtz a0, a0
481; RV64I-NEXT:    xori a0, a0, 1
482; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
483; RV64I-NEXT:    addi sp, sp, 16
484; RV64I-NEXT:    ret
485  %1 = fcmp ule float %a, %b
486  %2 = zext i1 %1 to i32
487  ret i32 %2
488}
489
490; FIXME: slli+srli on RV64 are unnecessary
491define i32 @fcmp_une(float %a, float %b) nounwind {
492; CHECKIF-LABEL: fcmp_une:
493; CHECKIF:       # %bb.0:
494; CHECKIF-NEXT:    feq.s a0, fa0, fa1
495; CHECKIF-NEXT:    xori a0, a0, 1
496; CHECKIF-NEXT:    ret
497;
498; RV32I-LABEL: fcmp_une:
499; RV32I:       # %bb.0:
500; RV32I-NEXT:    addi sp, sp, -16
501; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
502; RV32I-NEXT:    call __nesf2
503; RV32I-NEXT:    snez a0, a0
504; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
505; RV32I-NEXT:    addi sp, sp, 16
506; RV32I-NEXT:    ret
507;
508; RV64I-LABEL: fcmp_une:
509; RV64I:       # %bb.0:
510; RV64I-NEXT:    addi sp, sp, -16
511; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
512; RV64I-NEXT:    call __nesf2
513; RV64I-NEXT:    sext.w a0, a0
514; RV64I-NEXT:    snez a0, a0
515; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
516; RV64I-NEXT:    addi sp, sp, 16
517; RV64I-NEXT:    ret
518  %1 = fcmp une float %a, %b
519  %2 = zext i1 %1 to i32
520  ret i32 %2
521}
522
523; FIXME: slli+srli on RV64 are unnecessary
524define i32 @fcmp_uno(float %a, float %b) nounwind {
525; CHECKIF-LABEL: fcmp_uno:
526; CHECKIF:       # %bb.0:
527; CHECKIF-NEXT:    feq.s a0, fa0, fa0
528; CHECKIF-NEXT:    feq.s a1, fa1, fa1
529; CHECKIF-NEXT:    and a0, a0, a1
530; CHECKIF-NEXT:    xori a0, a0, 1
531; CHECKIF-NEXT:    ret
532;
533; RV32I-LABEL: fcmp_uno:
534; RV32I:       # %bb.0:
535; RV32I-NEXT:    addi sp, sp, -16
536; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
537; RV32I-NEXT:    call __unordsf2
538; RV32I-NEXT:    snez a0, a0
539; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
540; RV32I-NEXT:    addi sp, sp, 16
541; RV32I-NEXT:    ret
542;
543; RV64I-LABEL: fcmp_uno:
544; RV64I:       # %bb.0:
545; RV64I-NEXT:    addi sp, sp, -16
546; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
547; RV64I-NEXT:    call __unordsf2
548; RV64I-NEXT:    sext.w a0, a0
549; RV64I-NEXT:    snez a0, a0
550; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
551; RV64I-NEXT:    addi sp, sp, 16
552; RV64I-NEXT:    ret
553  %1 = fcmp uno float %a, %b
554  %2 = zext i1 %1 to i32
555  ret i32 %2
556}
557
558define i32 @fcmp_true(float %a, float %b) nounwind {
559; CHECKIF-LABEL: fcmp_true:
560; CHECKIF:       # %bb.0:
561; CHECKIF-NEXT:    li a0, 1
562; CHECKIF-NEXT:    ret
563;
564; RV32I-LABEL: fcmp_true:
565; RV32I:       # %bb.0:
566; RV32I-NEXT:    li a0, 1
567; RV32I-NEXT:    ret
568;
569; RV64I-LABEL: fcmp_true:
570; RV64I:       # %bb.0:
571; RV64I-NEXT:    li a0, 1
572; RV64I-NEXT:    ret
573  %1 = fcmp true float %a, %b
574  %2 = zext i1 %1 to i32
575  ret i32 %2
576}
577