xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip-rv64.ll (revision 0864501b97a70ce7d6f1741514fae08eef7c237e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m -global-isel -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefix=RV64IM
4
5define i64 @sll_i64(i64 %a, i64 %b) {
6; RV64IM-LABEL: sll_i64:
7; RV64IM:       # %bb.0: # %entry
8; RV64IM-NEXT:    sll a0, a0, a1
9; RV64IM-NEXT:    ret
10entry:
11  %0 = shl i64 %a, %b
12  ret i64 %0
13}
14
15define i64 @slli_i64(i64 %a) {
16; RV64IM-LABEL: slli_i64:
17; RV64IM:       # %bb.0: # %entry
18; RV64IM-NEXT:    slli a0, a0, 33
19; RV64IM-NEXT:    ret
20entry:
21  %0 = shl i64 %a, 33
22  ret i64 %0
23}
24
25define i64 @sra_i64(i64 %a, i64 %b) {
26; RV64IM-LABEL: sra_i64:
27; RV64IM:       # %bb.0: # %entry
28; RV64IM-NEXT:    sra a0, a0, a1
29; RV64IM-NEXT:    ret
30entry:
31  %0 = ashr i64 %a, %b
32  ret i64 %0
33}
34
35define i64 @srai_i64(i64 %a) {
36; RV64IM-LABEL: srai_i64:
37; RV64IM:       # %bb.0: # %entry
38; RV64IM-NEXT:    srai a0, a0, 47
39; RV64IM-NEXT:    ret
40entry:
41  %0 = ashr i64 %a, 47
42  ret i64 %0
43}
44
45define i64 @srl_i64(i64 %a, i64 %b) {
46; RV64IM-LABEL: srl_i64:
47; RV64IM:       # %bb.0: # %entry
48; RV64IM-NEXT:    srl a0, a0, a1
49; RV64IM-NEXT:    ret
50entry:
51  %0 = lshr i64 %a, %b
52  ret i64 %0
53}
54
55define i64 @srli_i64(i64 %a, i64 %b) {
56; RV64IM-LABEL: srli_i64:
57; RV64IM:       # %bb.0: # %entry
58; RV64IM-NEXT:    srli a0, a0, 55
59; RV64IM-NEXT:    ret
60entry:
61  %0 = lshr i64 %a, 55
62  ret i64 %0
63}
64
65define i64 @sdiv_i64(i64 %a, i64 %b) {
66; RV64IM-LABEL: sdiv_i64:
67; RV64IM:       # %bb.0: # %entry
68; RV64IM-NEXT:    div a0, a0, a1
69; RV64IM-NEXT:    ret
70entry:
71  %0 = sdiv i64 %a, %b
72  ret i64 %0
73}
74
75define i64 @srem_i64(i64 %a, i64 %b) {
76; RV64IM-LABEL: srem_i64:
77; RV64IM:       # %bb.0: # %entry
78; RV64IM-NEXT:    rem a0, a0, a1
79; RV64IM-NEXT:    ret
80entry:
81  %0 = srem i64 %a, %b
82  ret i64 %0
83}
84
85define i64 @udiv_i64(i64 %a, i64 %b) {
86; RV64IM-LABEL: udiv_i64:
87; RV64IM:       # %bb.0: # %entry
88; RV64IM-NEXT:    divu a0, a0, a1
89; RV64IM-NEXT:    ret
90entry:
91  %0 = udiv i64 %a, %b
92  ret i64 %0
93}
94
95define i64 @urem_i64(i64 %a, i64 %b) {
96; RV64IM-LABEL: urem_i64:
97; RV64IM:       # %bb.0: # %entry
98; RV64IM-NEXT:    remu a0, a0, a1
99; RV64IM-NEXT:    ret
100entry:
101  %0 = urem i64 %a, %b
102  ret i64 %0
103}
104
105define i64 @zext_nneg_i32_i64(i32 %a) {
106; RV64IM-LABEL: zext_nneg_i32_i64:
107; RV64IM:       # %bb.0: # %entry
108; RV64IM-NEXT:    sext.w a0, a0
109; RV64IM-NEXT:    ret
110entry:
111  %b = zext nneg i32 %a to i64
112  ret i64 %b
113}
114