xref: /llvm-project/llvm/test/CodeGen/PowerPC/widen-vec-correctly-be.ll (revision 8b6e9de3dd114db28fde892c67960a87d9870637)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
3; RUN:     -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN: FileCheck %s --check-prefix=CHECK-BE
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN: FileCheck %s --check-prefix=CHECK-P9-BE
8define void @test() local_unnamed_addr #0 align 2 {
9; CHECK-BE-LABEL: test:
10; CHECK-BE:       # %bb.0: # %bb
11; CHECK-BE-NEXT:    lhz r3, 0(r3)
12; CHECK-BE-NEXT:    vspltisw v2, -16
13; CHECK-BE-NEXT:    addi r3, r3, 1
14; CHECK-BE-NEXT:    xxlxor vs1, vs1, vs1
15; CHECK-BE-NEXT:    vsrw v2, v2, v2
16; CHECK-BE-NEXT:    sldi r3, r3, 48
17; CHECK-BE-NEXT:    std r3, -32(r1)
18; CHECK-BE-NEXT:    std r3, -24(r1)
19; CHECK-BE-NEXT:    addi r3, r1, -32
20; CHECK-BE-NEXT:    lxvw4x vs0, 0, r3
21; CHECK-BE-NEXT:    addi r3, r1, -16
22; CHECK-BE-NEXT:    xxsel vs0, vs0, vs1, v2
23; CHECK-BE-NEXT:    stxvw4x vs0, 0, r3
24; CHECK-BE-NEXT:    lwz r3, -16(r1)
25; CHECK-BE-NEXT:    stw r3, 0(r3)
26; CHECK-BE-NEXT:    .p2align 4
27; CHECK-BE-NEXT:  .LBB0_1: # %bb9
28; CHECK-BE-NEXT:    #
29; CHECK-BE-NEXT:    b .LBB0_1
30;
31; CHECK-P9-BE-LABEL: test:
32; CHECK-P9-BE:       # %bb.0: # %bb
33; CHECK-P9-BE-NEXT:    lhz r3, 0(r3)
34; CHECK-P9-BE-NEXT:    vspltisw v2, -16
35; CHECK-P9-BE-NEXT:    xxlxor vs0, vs0, vs0
36; CHECK-P9-BE-NEXT:    addi r3, r3, 1
37; CHECK-P9-BE-NEXT:    vsrw v2, v2, v2
38; CHECK-P9-BE-NEXT:    sldi r3, r3, 48
39; CHECK-P9-BE-NEXT:    mtfprd f1, r3
40; CHECK-P9-BE-NEXT:    xxsel v2, vs1, vs0, v2
41; CHECK-P9-BE-NEXT:    xxsldwi vs0, v2, v2, 3
42; CHECK-P9-BE-NEXT:    stfiwx f0, 0, r3
43; CHECK-P9-BE-NEXT:    .p2align 4
44; CHECK-P9-BE-NEXT:  .LBB0_1: # %bb9
45; CHECK-P9-BE-NEXT:    #
46; CHECK-P9-BE-NEXT:    b .LBB0_1
47bb:
48  br i1 false, label %bb1, label %bb2
49
50bb1:                                              ; preds = %bb
51  unreachable
52
53bb2:                                              ; preds = %bb
54  %i = load i32, ptr poison, align 4
55  %i3 = trunc i32 %i to i16
56  %i4 = add i16 %i3, 1
57  %i5 = bitcast i16 %i4 to <2 x i8>
58  %i6 = shufflevector <2 x i8> %i5, <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
59  %i7 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i8> %i6, <4 x i8> undef
60  %i8 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x i8> <i8 undef, i8 undef, i8 0, i8 0>, <4 x i8> %i7
61  br label %bb9
62
63bb9:                                              ; preds = %bb9, %bb2
64  %i10 = phi <4 x i8> [ %i8, %bb2 ], [ poison, %bb9 ]
65  %i11 = bitcast <4 x i8> %i10 to i32
66  store i32 %i11, ptr poison, align 2
67  br label %bb9
68}
69