1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s 3; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | \ 4; RUN: FileCheck -check-prefix=CHECK-FISL %s 5target datalayout = "E-m:e-i64:64-n32:64" 6target triple = "powerpc64-unknown-linux-gnu" 7 8declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0 9 10define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 { 11entry: 12 %ca = tail call <2 x double> @sv(<2 x double> %b, <2 x i64> %c, <4 x float> %a) 13 %v = fadd <2 x double> %ca, <double 1.0, double 1.0> 14 ret <2 x double> %v 15 16; CHECK-LABEL: @main 17; CHECK-DAG: vmr [[V:[0-9]+]], 2 18; CHECK-DAG: vmr 2, 3 19; CHECK-DAG: vmr 3, 4 20; CHECK-DAG: vmr 4, [[V]] 21; CHECK: bl sv 22; CHECK: lxvd2x [[VC:[0-9]+]], 23; CHECK: xvadddp 34, 34, [[VC]] 24; CHECK: blr 25 26; CHECK-FISL-LABEL: @main 27; CHECK-FISL: stxvd2x 36, 1, 3 28; CHECK-FISL: vmr 4, 3 29; CHECK-FISL: lxvd2x 35, 1, 3 30; CHECK-FISL: 3, 144 31; CHECK-FISL: stxvd2x 36, 1, 3 32; CHECK-FISL: vmr 4, 2 33; CHECK-FISL: bl sv 34 35; CHECK-FISL: lxvd2x [[VC:[0-9]+]], 36; CHECK-FISL: xvadddp 34, 34, [[VC]] 37; CHECK-FISL: blr 38} 39 40attributes #0 = { noinline nounwind readnone } 41attributes #1 = { nounwind } 42