1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \ 3; RUN: -verify-machineinstrs -mcpu=pwr8 < %s | \ 4; RUN: FileCheck --check-prefix=CHECK-P8 %s 5; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \ 6; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | \ 7; RUN: FileCheck --check-prefix=CHECK-P7 %s 8 9define <16 x i8> @rotl_v16i8(<16 x i8> %a) { 10; CHECK-P8-LABEL: rotl_v16i8: 11; CHECK-P8: # %bb.0: # %entry 12; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha 13; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l 14; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 15; CHECK-P8-NEXT: xxswapd vs35, vs0 16; CHECK-P8-NEXT: vrlb v2, v2, v3 17; CHECK-P8-NEXT: blr 18; 19; CHECK-P7-LABEL: rotl_v16i8: 20; CHECK-P7: # %bb.0: # %entry 21; CHECK-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha 22; CHECK-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l 23; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 24; CHECK-P7-NEXT: vrlb v2, v2, v3 25; CHECK-P7-NEXT: blr 26entry: 27 %b = shl <16 x i8> %a, <i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7, i8 8, i8 8> 28 %c = lshr <16 x i8> %a, <i8 7, i8 7, i8 6, i8 6, i8 5, i8 5, i8 4, i8 4, i8 3, i8 3, i8 2, i8 2, i8 1, i8 1, i8 0, i8 0> 29 %d = or <16 x i8> %b, %c 30 ret <16 x i8> %d 31} 32 33define <8 x i16> @rotl_v8i16(<8 x i16> %a) { 34; CHECK-P8-LABEL: rotl_v8i16: 35; CHECK-P8: # %bb.0: # %entry 36; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha 37; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l 38; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 39; CHECK-P8-NEXT: xxswapd vs35, vs0 40; CHECK-P8-NEXT: vrlh v2, v2, v3 41; CHECK-P8-NEXT: blr 42; 43; CHECK-P7-LABEL: rotl_v8i16: 44; CHECK-P7: # %bb.0: # %entry 45; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha 46; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l 47; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 48; CHECK-P7-NEXT: vrlh v2, v2, v3 49; CHECK-P7-NEXT: blr 50entry: 51 %b = shl <8 x i16> %a, <i16 1, i16 2, i16 3, i16 5, i16 7, i16 11, i16 13, i16 16> 52 %c = lshr <8 x i16> %a, <i16 15, i16 14, i16 13, i16 11, i16 9, i16 5, i16 3, i16 0> 53 %d = or <8 x i16> %b, %c 54 ret <8 x i16> %d 55} 56 57define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) { 58; CHECK-P8-LABEL: rotl_v4i32_0: 59; CHECK-P8: # %bb.0: # %entry 60; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha 61; CHECK-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l 62; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 63; CHECK-P8-NEXT: xxswapd vs35, vs0 64; CHECK-P8-NEXT: vrlw v2, v2, v3 65; CHECK-P8-NEXT: blr 66; 67; CHECK-P7-LABEL: rotl_v4i32_0: 68; CHECK-P7: # %bb.0: # %entry 69; CHECK-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha 70; CHECK-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l 71; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 72; CHECK-P7-NEXT: vrlw v2, v2, v3 73; CHECK-P7-NEXT: blr 74entry: 75 %b = shl <4 x i32> %a, <i32 29, i32 19, i32 17, i32 11> 76 %c = lshr <4 x i32> %a, <i32 3, i32 13, i32 15, i32 21> 77 %d = or <4 x i32> %b, %c 78 ret <4 x i32> %d 79} 80 81define <4 x i32> @rotl_v4i32_1(<4 x i32> %a) { 82; CHECK-P8-LABEL: rotl_v4i32_1: 83; CHECK-P8: # %bb.0: # %entry 84; CHECK-P8-NEXT: vspltisw v3, -16 85; CHECK-P8-NEXT: vspltisw v4, 7 86; CHECK-P8-NEXT: vsubuwm v3, v4, v3 87; CHECK-P8-NEXT: vrlw v2, v2, v3 88; CHECK-P8-NEXT: blr 89; 90; CHECK-P7-LABEL: rotl_v4i32_1: 91; CHECK-P7: # %bb.0: # %entry 92; CHECK-P7-NEXT: vspltisw v3, -16 93; CHECK-P7-NEXT: vspltisw v4, 7 94; CHECK-P7-NEXT: vsubuwm v3, v4, v3 95; CHECK-P7-NEXT: vrlw v2, v2, v3 96; CHECK-P7-NEXT: blr 97entry: 98 %b = shl <4 x i32> %a, <i32 23, i32 23, i32 23, i32 23> 99 %c = lshr <4 x i32> %a, <i32 9, i32 9, i32 9, i32 9> 100 %d = or <4 x i32> %b, %c 101 ret <4 x i32> %d 102} 103 104define <2 x i64> @rotl_v2i64(<2 x i64> %a) { 105; CHECK-P8-LABEL: rotl_v2i64: 106; CHECK-P8: # %bb.0: # %entry 107; CHECK-P8-NEXT: addis r3, r2, .LCPI4_0@toc@ha 108; CHECK-P8-NEXT: addi r3, r3, .LCPI4_0@toc@l 109; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 110; CHECK-P8-NEXT: xxswapd vs35, vs0 111; CHECK-P8-NEXT: vrld v2, v2, v3 112; CHECK-P8-NEXT: blr 113; 114; CHECK-P7-LABEL: rotl_v2i64: 115; CHECK-P7: # %bb.0: # %entry 116; CHECK-P7-NEXT: addi r3, r1, -32 117; CHECK-P7-NEXT: stxvd2x vs34, 0, r3 118; CHECK-P7-NEXT: ld r3, -24(r1) 119; CHECK-P7-NEXT: rotldi r3, r3, 53 120; CHECK-P7-NEXT: std r3, -8(r1) 121; CHECK-P7-NEXT: ld r3, -32(r1) 122; CHECK-P7-NEXT: rotldi r3, r3, 41 123; CHECK-P7-NEXT: std r3, -16(r1) 124; CHECK-P7-NEXT: addi r3, r1, -16 125; CHECK-P7-NEXT: lxvd2x vs34, 0, r3 126; CHECK-P7-NEXT: blr 127entry: 128 %b = shl <2 x i64> %a, <i64 41, i64 53> 129 %c = lshr <2 x i64> %a, <i64 23, i64 11> 130 %d = or <2 x i64> %b, %c 131 ret <2 x i64> %d 132} 133