xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec_shuffle_le.ll (revision 5403c59c608c08c8ecd4303763f08eb046eb5e4d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
3
4define void @VPKUHUM_xy(ptr %A, ptr %B) {
5; CHECK-LABEL: VPKUHUM_xy:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    lvx 2, 0, 3
8; CHECK-NEXT:    lvx 3, 0, 4
9; CHECK-NEXT:    vpkuhum 2, 3, 2
10; CHECK-NEXT:    stvx 2, 0, 3
11; CHECK-NEXT:    blr
12entry:
13        %tmp = load <16 x i8>, ptr %A
14        %tmp2 = load <16 x i8>, ptr %B
15        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
16        store <16 x i8> %tmp3, ptr %A
17        ret void
18}
19
20define void @VPKUHUM_xx(ptr %A) {
21; CHECK-LABEL: VPKUHUM_xx:
22; CHECK:       # %bb.0: # %entry
23; CHECK-NEXT:    lvx 2, 0, 3
24; CHECK-NEXT:    vpkuhum 2, 2, 2
25; CHECK-NEXT:    stvx 2, 0, 3
26; CHECK-NEXT:    blr
27entry:
28        %tmp = load <16 x i8>, ptr %A
29        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
30        store <16 x i8> %tmp2, ptr %A
31        ret void
32}
33
34define void @VPKUWUM_xy(ptr %A, ptr %B) {
35; CHECK-LABEL: VPKUWUM_xy:
36; CHECK:       # %bb.0: # %entry
37; CHECK-NEXT:    lvx 2, 0, 3
38; CHECK-NEXT:    lvx 3, 0, 4
39; CHECK-NEXT:    vpkuwum 2, 3, 2
40; CHECK-NEXT:    stvx 2, 0, 3
41; CHECK-NEXT:    blr
42entry:
43        %tmp = load <16 x i8>, ptr %A
44        %tmp2 = load <16 x i8>, ptr %B
45        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
46        store <16 x i8> %tmp3, ptr %A
47        ret void
48}
49
50define void @VPKUWUM_xx(ptr %A) {
51; CHECK-LABEL: VPKUWUM_xx:
52; CHECK:       # %bb.0: # %entry
53; CHECK-NEXT:    lvx 2, 0, 3
54; CHECK-NEXT:    vpkuwum 2, 2, 2
55; CHECK-NEXT:    stvx 2, 0, 3
56; CHECK-NEXT:    blr
57entry:
58        %tmp = load <16 x i8>, ptr %A
59        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
60        store <16 x i8> %tmp2, ptr %A
61        ret void
62}
63
64define void @VMRGLB_xy(ptr %A, ptr %B) {
65; CHECK-LABEL: VMRGLB_xy:
66; CHECK:       # %bb.0: # %entry
67; CHECK-NEXT:    lvx 2, 0, 3
68; CHECK-NEXT:    lvx 3, 0, 4
69; CHECK-NEXT:    vmrglb 2, 3, 2
70; CHECK-NEXT:    stvx 2, 0, 3
71; CHECK-NEXT:    blr
72entry:
73        %tmp = load <16 x i8>, ptr %A
74        %tmp2 = load <16 x i8>, ptr %B
75        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
76        store <16 x i8> %tmp3, ptr %A
77        ret void
78}
79
80define void @VMRGLB_xx(ptr %A) {
81; CHECK-LABEL: VMRGLB_xx:
82; CHECK:       # %bb.0: # %entry
83; CHECK-NEXT:    lvx 2, 0, 3
84; CHECK-NEXT:    vmrglb 2, 2, 2
85; CHECK-NEXT:    stvx 2, 0, 3
86; CHECK-NEXT:    blr
87entry:
88        %tmp = load <16 x i8>, ptr %A
89        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
90        store <16 x i8> %tmp2, ptr %A
91        ret void
92}
93
94define void @VMRGHB_xy(ptr %A, ptr %B) {
95; CHECK-LABEL: VMRGHB_xy:
96; CHECK:       # %bb.0: # %entry
97; CHECK-NEXT:    lvx 2, 0, 3
98; CHECK-NEXT:    lvx 3, 0, 4
99; CHECK-NEXT:    vmrghb 2, 3, 2
100; CHECK-NEXT:    stvx 2, 0, 3
101; CHECK-NEXT:    blr
102entry:
103        %tmp = load <16 x i8>, ptr %A
104        %tmp2 = load <16 x i8>, ptr %B
105        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
106        store <16 x i8> %tmp3, ptr %A
107        ret void
108}
109
110define void @VMRGHB_xx(ptr %A) {
111; CHECK-LABEL: VMRGHB_xx:
112; CHECK:       # %bb.0: # %entry
113; CHECK-NEXT:    lvx 2, 0, 3
114; CHECK-NEXT:    vmrghb 2, 2, 2
115; CHECK-NEXT:    stvx 2, 0, 3
116; CHECK-NEXT:    blr
117entry:
118        %tmp = load <16 x i8>, ptr %A
119        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
120        store <16 x i8> %tmp2, ptr %A
121        ret void
122}
123
124define void @VMRGLH_xy(ptr %A, ptr %B) {
125; CHECK-LABEL: VMRGLH_xy:
126; CHECK:       # %bb.0: # %entry
127; CHECK-NEXT:    lvx 2, 0, 3
128; CHECK-NEXT:    lvx 3, 0, 4
129; CHECK-NEXT:    vmrglh 2, 3, 2
130; CHECK-NEXT:    stvx 2, 0, 3
131; CHECK-NEXT:    blr
132entry:
133        %tmp = load <16 x i8>, ptr %A
134        %tmp2 = load <16 x i8>, ptr %B
135        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
136        store <16 x i8> %tmp3, ptr %A
137        ret void
138}
139
140define void @VMRGLH_xx(ptr %A) {
141; CHECK-LABEL: VMRGLH_xx:
142; CHECK:       # %bb.0: # %entry
143; CHECK-NEXT:    lvx 2, 0, 3
144; CHECK-NEXT:    vmrglh 2, 2, 2
145; CHECK-NEXT:    stvx 2, 0, 3
146; CHECK-NEXT:    blr
147entry:
148        %tmp = load <16 x i8>, ptr %A
149        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
150        store <16 x i8> %tmp2, ptr %A
151        ret void
152}
153
154define void @VMRGHH_xy(ptr %A, ptr %B) {
155; CHECK-LABEL: VMRGHH_xy:
156; CHECK:       # %bb.0: # %entry
157; CHECK-NEXT:    lvx 2, 0, 3
158; CHECK-NEXT:    lvx 3, 0, 4
159; CHECK-NEXT:    vmrghh 2, 3, 2
160; CHECK-NEXT:    stvx 2, 0, 3
161; CHECK-NEXT:    blr
162entry:
163        %tmp = load <16 x i8>, ptr %A
164        %tmp2 = load <16 x i8>, ptr %B
165        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
166        store <16 x i8> %tmp3, ptr %A
167        ret void
168}
169
170define void @VMRGHH_xx(ptr %A) {
171; CHECK-LABEL: VMRGHH_xx:
172; CHECK:       # %bb.0: # %entry
173; CHECK-NEXT:    lvx 2, 0, 3
174; CHECK-NEXT:    vmrghh 2, 2, 2
175; CHECK-NEXT:    stvx 2, 0, 3
176; CHECK-NEXT:    blr
177entry:
178        %tmp = load <16 x i8>, ptr %A
179        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
180        store <16 x i8> %tmp2, ptr %A
181        ret void
182}
183
184define void @VMRGLW_xy(ptr %A, ptr %B) {
185; CHECK-LABEL: VMRGLW_xy:
186; CHECK:       # %bb.0: # %entry
187; CHECK-NEXT:    lvx 2, 0, 3
188; CHECK-NEXT:    lvx 3, 0, 4
189; CHECK-NEXT:    vmrglw 2, 3, 2
190; CHECK-NEXT:    stvx 2, 0, 3
191; CHECK-NEXT:    blr
192entry:
193        %tmp = load <16 x i8>, ptr %A
194        %tmp2 = load <16 x i8>, ptr %B
195        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
196        store <16 x i8> %tmp3, ptr %A
197        ret void
198}
199
200define void @VMRGLW_xx(ptr %A) {
201; CHECK-LABEL: VMRGLW_xx:
202; CHECK:       # %bb.0: # %entry
203; CHECK-NEXT:    lvx 2, 0, 3
204; CHECK-NEXT:    vmrglw 2, 2, 2
205; CHECK-NEXT:    stvx 2, 0, 3
206; CHECK-NEXT:    blr
207entry:
208        %tmp = load <16 x i8>, ptr %A
209        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
210        store <16 x i8> %tmp2, ptr %A
211        ret void
212}
213
214define void @VMRGHW_xy(ptr %A, ptr %B) {
215; CHECK-LABEL: VMRGHW_xy:
216; CHECK:       # %bb.0: # %entry
217; CHECK-NEXT:    lvx 2, 0, 3
218; CHECK-NEXT:    lvx 3, 0, 4
219; CHECK-NEXT:    vmrghw 2, 3, 2
220; CHECK-NEXT:    stvx 2, 0, 3
221; CHECK-NEXT:    blr
222entry:
223        %tmp = load <16 x i8>, ptr %A
224        %tmp2 = load <16 x i8>, ptr %B
225        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
226        store <16 x i8> %tmp3, ptr %A
227        ret void
228}
229
230define void @VMRGHW_xx(ptr %A) {
231; CHECK-LABEL: VMRGHW_xx:
232; CHECK:       # %bb.0: # %entry
233; CHECK-NEXT:    lvx 2, 0, 3
234; CHECK-NEXT:    vmrghw 2, 2, 2
235; CHECK-NEXT:    stvx 2, 0, 3
236; CHECK-NEXT:    blr
237entry:
238        %tmp = load <16 x i8>, ptr %A
239        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
240        store <16 x i8> %tmp2, ptr %A
241        ret void
242}
243
244define void @VSLDOI_xy(ptr %A, ptr %B) {
245; CHECK-LABEL: VSLDOI_xy:
246; CHECK:       # %bb.0: # %entry
247; CHECK-NEXT:    lvx 2, 0, 3
248; CHECK-NEXT:    lvx 3, 0, 4
249; CHECK-NEXT:    vsldoi 2, 3, 2, 4
250; CHECK-NEXT:    stvx 2, 0, 3
251; CHECK-NEXT:    blr
252entry:
253        %tmp = load <16 x i8>, ptr %A
254        %tmp2 = load <16 x i8>, ptr %B
255        %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
256        store <16 x i8> %tmp3, ptr %A
257        ret void
258}
259
260define void @VSLDOI_xx(ptr %A) {
261; CHECK-LABEL: VSLDOI_xx:
262; CHECK:       # %bb.0: # %entry
263; CHECK-NEXT:    lvx 2, 0, 3
264; CHECK-NEXT:    vsldoi 2, 2, 2, 4
265; CHECK-NEXT:    stvx 2, 0, 3
266; CHECK-NEXT:    blr
267entry:
268        %tmp = load <16 x i8>, ptr %A
269        %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
270        store <16 x i8> %tmp2, ptr %A
271        ret void
272}
273
274