xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec_int_to_double_shuffle.ll (revision 666ee849f0778160b4660acccb796ac5bd238b2d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
3; RUN:   -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LE %s
4; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown \
5; RUN:   -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-BE %s
6
7define <2 x double> @foo(<4 x i32> %s) {
8; CHECK-LE-LABEL: foo:
9; CHECK-LE:       # %bb.0: # %entry
10; CHECK-LE-NEXT:    xvcvsxwdp 34, 34
11; CHECK-LE-NEXT:    blr
12;
13; CHECK-BE-LABEL: foo:
14; CHECK-BE:       # %bb.0: # %entry
15; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 1
16; CHECK-BE-NEXT:    xvcvsxwdp 34, 0
17; CHECK-BE-NEXT:    blr
18entry:
19  %0 = shufflevector <4 x i32> %s, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
20  %1 = sitofp <2 x i32> %0 to <2 x double>
21  ret <2 x double> %1
22}
23
24define <2 x double> @bar(<4 x i32> %s) {
25; CHECK-LE-LABEL: bar:
26; CHECK-LE:       # %bb.0: # %entry
27; CHECK-LE-NEXT:    xvcvuxwdp 34, 34
28; CHECK-LE-NEXT:    blr
29;
30; CHECK-BE-LABEL: bar:
31; CHECK-BE:       # %bb.0: # %entry
32; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 1
33; CHECK-BE-NEXT:    xvcvuxwdp 34, 0
34; CHECK-BE-NEXT:    blr
35entry:
36  %0 = shufflevector <4 x i32> %s, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
37  %1 = uitofp <2 x i32> %0 to <2 x double>
38  ret <2 x double> %1
39}
40