xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec_int_ext.ll (revision 934d5fa2b8672695c335deed0e19d0e777c98403)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
4
5define <4 x i32> @vextsb2wLE(<16 x i8> %a) {
6; CHECK-LE-LABEL: vextsb2wLE:
7; CHECK-LE:       # %bb.0: # %entry
8; CHECK-LE-NEXT:    vextsb2w 2, 2
9; CHECK-LE-NEXT:    blr
10;
11; CHECK-BE-LABEL: vextsb2wLE:
12; CHECK-BE:       # %bb.0: # %entry
13; CHECK-BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
14; CHECK-BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
15; CHECK-BE-NEXT:    lxv 0, 0(3)
16; CHECK-BE-NEXT:    xxperm 34, 34, 0
17; CHECK-BE-NEXT:    vextsb2w 2, 2
18; CHECK-BE-NEXT:    blr
19
20entry:
21  %vecext = extractelement <16 x i8> %a, i32 0
22  %conv = sext i8 %vecext to i32
23  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
24  %vecext1 = extractelement <16 x i8> %a, i32 4
25  %conv2 = sext i8 %vecext1 to i32
26  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
27  %vecext4 = extractelement <16 x i8> %a, i32 8
28  %conv5 = sext i8 %vecext4 to i32
29  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
30  %vecext7 = extractelement <16 x i8> %a, i32 12
31  %conv8 = sext i8 %vecext7 to i32
32  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
33  ret <4 x i32> %vecinit9
34}
35
36define <2 x i64> @vextsb2dLE(<16 x i8> %a) {
37; CHECK-LE-LABEL: vextsb2dLE:
38; CHECK-LE:       # %bb.0: # %entry
39; CHECK-LE-NEXT:    vextsb2d 2, 2
40; CHECK-LE-NEXT:    blr
41;
42; CHECK-BE-LABEL: vextsb2dLE:
43; CHECK-BE:       # %bb.0: # %entry
44; CHECK-BE-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
45; CHECK-BE-NEXT:    addi 3, 3, .LCPI1_0@toc@l
46; CHECK-BE-NEXT:    lxv 0, 0(3)
47; CHECK-BE-NEXT:    xxperm 34, 34, 0
48; CHECK-BE-NEXT:    vextsb2d 2, 2
49; CHECK-BE-NEXT:    blr
50
51entry:
52  %vecext = extractelement <16 x i8> %a, i32 0
53  %conv = sext i8 %vecext to i64
54  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
55  %vecext1 = extractelement <16 x i8> %a, i32 8
56  %conv2 = sext i8 %vecext1 to i64
57  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
58  ret <2 x i64> %vecinit3
59}
60
61define <4 x i32> @vextsh2wLE(<8 x i16> %a) {
62; CHECK-LE-LABEL: vextsh2wLE:
63; CHECK-LE:       # %bb.0: # %entry
64; CHECK-LE-NEXT:    vextsh2w 2, 2
65; CHECK-LE-NEXT:    blr
66;
67; CHECK-BE-LABEL: vextsh2wLE:
68; CHECK-BE:       # %bb.0: # %entry
69; CHECK-BE-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
70; CHECK-BE-NEXT:    addi 3, 3, .LCPI2_0@toc@l
71; CHECK-BE-NEXT:    lxv 0, 0(3)
72; CHECK-BE-NEXT:    xxperm 34, 34, 0
73; CHECK-BE-NEXT:    vextsh2w 2, 2
74; CHECK-BE-NEXT:    blr
75
76entry:
77  %vecext = extractelement <8 x i16> %a, i32 0
78  %conv = sext i16 %vecext to i32
79  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
80  %vecext1 = extractelement <8 x i16> %a, i32 2
81  %conv2 = sext i16 %vecext1 to i32
82  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
83  %vecext4 = extractelement <8 x i16> %a, i32 4
84  %conv5 = sext i16 %vecext4 to i32
85  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
86  %vecext7 = extractelement <8 x i16> %a, i32 6
87  %conv8 = sext i16 %vecext7 to i32
88  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
89  ret <4 x i32> %vecinit9
90}
91
92define <2 x i64> @vextsh2dLE(<8 x i16> %a) {
93; CHECK-LE-LABEL: vextsh2dLE:
94; CHECK-LE:       # %bb.0: # %entry
95; CHECK-LE-NEXT:    vextsh2d 2, 2
96; CHECK-LE-NEXT:    blr
97;
98; CHECK-BE-LABEL: vextsh2dLE:
99; CHECK-BE:       # %bb.0: # %entry
100; CHECK-BE-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
101; CHECK-BE-NEXT:    addi 3, 3, .LCPI3_0@toc@l
102; CHECK-BE-NEXT:    lxv 0, 0(3)
103; CHECK-BE-NEXT:    xxperm 34, 34, 0
104; CHECK-BE-NEXT:    vextsh2d 2, 2
105; CHECK-BE-NEXT:    blr
106
107entry:
108  %vecext = extractelement <8 x i16> %a, i32 0
109  %conv = sext i16 %vecext to i64
110  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
111  %vecext1 = extractelement <8 x i16> %a, i32 4
112  %conv2 = sext i16 %vecext1 to i64
113  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
114  ret <2 x i64> %vecinit3
115}
116
117define <2 x i64> @vextsw2dLE(<4 x i32> %a) {
118; CHECK-LE-LABEL: vextsw2dLE:
119; CHECK-LE:       # %bb.0: # %entry
120; CHECK-LE-NEXT:    vextsw2d 2, 2
121; CHECK-LE-NEXT:    blr
122;
123; CHECK-BE-LABEL: vextsw2dLE:
124; CHECK-BE:       # %bb.0: # %entry
125; CHECK-BE-NEXT:    vmrgew 2, 2, 2
126; CHECK-BE-NEXT:    vextsw2d 2, 2
127; CHECK-BE-NEXT:    blr
128
129entry:
130  %vecext = extractelement <4 x i32> %a, i32 0
131  %conv = sext i32 %vecext to i64
132  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
133  %vecext1 = extractelement <4 x i32> %a, i32 2
134  %conv2 = sext i32 %vecext1 to i64
135  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
136  ret <2 x i64> %vecinit3
137}
138
139define <4 x i32> @vextsb2wBE(<16 x i8> %a) {
140; CHECK-LE-LABEL: vextsb2wBE:
141; CHECK-LE:       # %bb.0: # %entry
142; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 13
143; CHECK-LE-NEXT:    vextsb2w 2, 2
144; CHECK-LE-NEXT:    blr
145;
146; CHECK-BE-LABEL: vextsb2wBE:
147; CHECK-BE:       # %bb.0: # %entry
148; CHECK-BE-NEXT:    vextsb2w 2, 2
149; CHECK-BE-NEXT:    blr
150entry:
151  %vecext = extractelement <16 x i8> %a, i32 3
152  %conv = sext i8 %vecext to i32
153  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
154  %vecext1 = extractelement <16 x i8> %a, i32 7
155  %conv2 = sext i8 %vecext1 to i32
156  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
157  %vecext4 = extractelement <16 x i8> %a, i32 11
158  %conv5 = sext i8 %vecext4 to i32
159  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
160  %vecext7 = extractelement <16 x i8> %a, i32 15
161  %conv8 = sext i8 %vecext7 to i32
162  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
163  ret <4 x i32> %vecinit9
164}
165
166define <2 x i64> @vextsb2dBE(<16 x i8> %a) {
167; CHECK-LE-LABEL: vextsb2dBE:
168; CHECK-LE:       # %bb.0: # %entry
169; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 9
170; CHECK-LE-NEXT:    vextsb2d 2, 2
171; CHECK-LE-NEXT:    blr
172;
173; CHECK-BE-LABEL: vextsb2dBE:
174; CHECK-BE:       # %bb.0: # %entry
175; CHECK-BE-NEXT:    vextsb2d 2, 2
176; CHECK-BE-NEXT:    blr
177entry:
178  %vecext = extractelement <16 x i8> %a, i32 7
179  %conv = sext i8 %vecext to i64
180  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
181  %vecext1 = extractelement <16 x i8> %a, i32 15
182  %conv2 = sext i8 %vecext1 to i64
183  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
184  ret <2 x i64> %vecinit3
185}
186
187define <4 x i32> @vextsh2wBE(<8 x i16> %a) {
188; CHECK-LE-LABEL: vextsh2wBE:
189; CHECK-LE:       # %bb.0: # %entry
190; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 14
191; CHECK-LE-NEXT:    vextsh2w 2, 2
192; CHECK-LE-NEXT:    blr
193;
194; CHECK-BE-LABEL: vextsh2wBE:
195; CHECK-BE:       # %bb.0: # %entry
196; CHECK-BE-NEXT:    vextsh2w 2, 2
197; CHECK-BE-NEXT:    blr
198entry:
199  %vecext = extractelement <8 x i16> %a, i32 1
200  %conv = sext i16 %vecext to i32
201  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
202  %vecext1 = extractelement <8 x i16> %a, i32 3
203  %conv2 = sext i16 %vecext1 to i32
204  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
205  %vecext4 = extractelement <8 x i16> %a, i32 5
206  %conv5 = sext i16 %vecext4 to i32
207  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
208  %vecext7 = extractelement <8 x i16> %a, i32 7
209  %conv8 = sext i16 %vecext7 to i32
210  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
211  ret <4 x i32> %vecinit9
212}
213
214define <2 x i64> @vextsh2dBE(<8 x i16> %a) {
215; CHECK-LE-LABEL: vextsh2dBE:
216; CHECK-LE:       # %bb.0: # %entry
217; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 10
218; CHECK-LE-NEXT:    vextsh2d 2, 2
219; CHECK-LE-NEXT:    blr
220;
221; CHECK-BE-LABEL: vextsh2dBE:
222; CHECK-BE:       # %bb.0: # %entry
223; CHECK-BE-NEXT:    vextsh2d 2, 2
224; CHECK-BE-NEXT:    blr
225entry:
226  %vecext = extractelement <8 x i16> %a, i32 3
227  %conv = sext i16 %vecext to i64
228  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
229  %vecext1 = extractelement <8 x i16> %a, i32 7
230  %conv2 = sext i16 %vecext1 to i64
231  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
232  ret <2 x i64> %vecinit3
233}
234
235define <2 x i64> @vextsw2dBE(<4 x i32> %a) {
236; CHECK-LE-LABEL: vextsw2dBE:
237; CHECK-LE:       # %bb.0: # %entry
238; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 12
239; CHECK-LE-NEXT:    vextsw2d 2, 2
240; CHECK-LE-NEXT:    blr
241;
242; CHECK-BE-LABEL: vextsw2dBE:
243; CHECK-BE:       # %bb.0: # %entry
244; CHECK-BE-NEXT:    vextsw2d 2, 2
245; CHECK-BE-NEXT:    blr
246entry:
247  %vecext = extractelement <4 x i32> %a, i32 1
248  %conv = sext i32 %vecext to i64
249  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
250  %vecext1 = extractelement <4 x i32> %a, i32 3
251  %conv2 = sext i32 %vecext1 to i64
252  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
253  ret <2 x i64> %vecinit3
254}
255
256define <2 x i64> @vextDiffVectors(<4 x i32> %a, <4 x i32> %b) {
257; CHECK-LE-LABEL: vextDiffVectors:
258; CHECK-LE:       # %bb.0: # %entry
259; CHECK-LE-NEXT:    li 3, 0
260; CHECK-LE-NEXT:    mfvsrwz 4, 35
261; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
262; CHECK-LE-NEXT:    extsw 4, 4
263; CHECK-LE-NEXT:    extsw 3, 3
264; CHECK-LE-NEXT:    mtvsrdd 34, 4, 3
265; CHECK-LE-NEXT:    blr
266;
267; CHECK-BE-LABEL: vextDiffVectors:
268; CHECK-BE:       # %bb.0: # %entry
269; CHECK-BE-NEXT:    li 3, 0
270; CHECK-BE-NEXT:    li 4, 8
271; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
272; CHECK-BE-NEXT:    vextuwlx 4, 4, 3
273; CHECK-BE-NEXT:    extsw 3, 3
274; CHECK-BE-NEXT:    extsw 4, 4
275; CHECK-BE-NEXT:    mtvsrdd 34, 3, 4
276; CHECK-BE-NEXT:    blr
277
278entry:
279  %vecext = extractelement <4 x i32> %a, i32 0
280  %conv = sext i32 %vecext to i64
281  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
282  %vecext1 = extractelement <4 x i32> %b, i32 2
283  %conv2 = sext i32 %vecext1 to i64
284  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
285  ret <2 x i64> %vecinit3
286}
287
288define <8 x i16> @testInvalidExtend(<16 x i8> %a) {
289; CHECK-LE-LABEL: testInvalidExtend:
290; CHECK-LE:       # %bb.0: # %entry
291; CHECK-LE-NEXT:    li 3, 0
292; CHECK-LE-NEXT:    li 4, 2
293; CHECK-LE-NEXT:    li 5, 4
294; CHECK-LE-NEXT:    li 6, 6
295; CHECK-LE-NEXT:    vextubrx 3, 3, 2
296; CHECK-LE-NEXT:    vextubrx 4, 4, 2
297; CHECK-LE-NEXT:    vextubrx 5, 5, 2
298; CHECK-LE-NEXT:    vextubrx 6, 6, 2
299; CHECK-LE-NEXT:    li 7, 8
300; CHECK-LE-NEXT:    li 8, 10
301; CHECK-LE-NEXT:    li 9, 12
302; CHECK-LE-NEXT:    li 10, 14
303; CHECK-LE-NEXT:    extsb 3, 3
304; CHECK-LE-NEXT:    extsb 4, 4
305; CHECK-LE-NEXT:    extsb 5, 5
306; CHECK-LE-NEXT:    extsb 6, 6
307; CHECK-LE-NEXT:    vextubrx 7, 7, 2
308; CHECK-LE-NEXT:    vextubrx 8, 8, 2
309; CHECK-LE-NEXT:    extsb 7, 7
310; CHECK-LE-NEXT:    extsb 8, 8
311; CHECK-LE-NEXT:    mtvsrd 35, 4
312; CHECK-LE-NEXT:    vextubrx 9, 9, 2
313; CHECK-LE-NEXT:    vextubrx 10, 10, 2
314; CHECK-LE-NEXT:    mtvsrd 34, 3
315; CHECK-LE-NEXT:    mtvsrd 36, 6
316; CHECK-LE-NEXT:    extsb 9, 9
317; CHECK-LE-NEXT:    extsb 10, 10
318; CHECK-LE-NEXT:    vmrghh 2, 3, 2
319; CHECK-LE-NEXT:    mtvsrd 35, 5
320; CHECK-LE-NEXT:    vmrghh 3, 4, 3
321; CHECK-LE-NEXT:    mtvsrd 36, 10
322; CHECK-LE-NEXT:    xxmrglw 0, 35, 34
323; CHECK-LE-NEXT:    mtvsrd 34, 7
324; CHECK-LE-NEXT:    mtvsrd 35, 8
325; CHECK-LE-NEXT:    vmrghh 2, 3, 2
326; CHECK-LE-NEXT:    mtvsrd 35, 9
327; CHECK-LE-NEXT:    vmrghh 3, 4, 3
328; CHECK-LE-NEXT:    xxmrglw 1, 35, 34
329; CHECK-LE-NEXT:    xxmrgld 34, 1, 0
330; CHECK-LE-NEXT:    blr
331;
332; CHECK-BE-LABEL: testInvalidExtend:
333; CHECK-BE:       # %bb.0: # %entry
334; CHECK-BE-NEXT:    li 9, 12
335; CHECK-BE-NEXT:    li 10, 14
336; CHECK-BE-NEXT:    li 7, 8
337; CHECK-BE-NEXT:    li 8, 10
338; CHECK-BE-NEXT:    vextublx 9, 9, 2
339; CHECK-BE-NEXT:    vextublx 10, 10, 2
340; CHECK-BE-NEXT:    vextublx 7, 7, 2
341; CHECK-BE-NEXT:    vextublx 8, 8, 2
342; CHECK-BE-NEXT:    li 5, 4
343; CHECK-BE-NEXT:    li 6, 6
344; CHECK-BE-NEXT:    li 3, 0
345; CHECK-BE-NEXT:    li 4, 2
346; CHECK-BE-NEXT:    extsb 9, 9
347; CHECK-BE-NEXT:    extsb 10, 10
348; CHECK-BE-NEXT:    extsb 7, 7
349; CHECK-BE-NEXT:    extsb 8, 8
350; CHECK-BE-NEXT:    vextublx 5, 5, 2
351; CHECK-BE-NEXT:    vextublx 6, 6, 2
352; CHECK-BE-NEXT:    extsb 5, 5
353; CHECK-BE-NEXT:    extsb 6, 6
354; CHECK-BE-NEXT:    mtfprwz 1, 9
355; CHECK-BE-NEXT:    addis 9, 2, .LCPI11_0@toc@ha
356; CHECK-BE-NEXT:    mtfprwz 0, 10
357; CHECK-BE-NEXT:    mtfprwz 3, 7
358; CHECK-BE-NEXT:    vextublx 3, 3, 2
359; CHECK-BE-NEXT:    extsb 3, 3
360; CHECK-BE-NEXT:    mtfprwz 4, 3
361; CHECK-BE-NEXT:    addi 9, 9, .LCPI11_0@toc@l
362; CHECK-BE-NEXT:    vextublx 4, 4, 2
363; CHECK-BE-NEXT:    extsb 4, 4
364; CHECK-BE-NEXT:    lxv 2, 0(9)
365; CHECK-BE-NEXT:    xxperm 0, 1, 2
366; CHECK-BE-NEXT:    mtfprwz 1, 8
367; CHECK-BE-NEXT:    xxperm 1, 3, 2
368; CHECK-BE-NEXT:    mtfprwz 3, 5
369; CHECK-BE-NEXT:    xxmrghw 0, 1, 0
370; CHECK-BE-NEXT:    mtfprwz 1, 6
371; CHECK-BE-NEXT:    xxperm 1, 3, 2
372; CHECK-BE-NEXT:    mtfprwz 3, 4
373; CHECK-BE-NEXT:    xxperm 3, 4, 2
374; CHECK-BE-NEXT:    xxmrghw 1, 3, 1
375; CHECK-BE-NEXT:    xxmrghd 34, 1, 0
376; CHECK-BE-NEXT:    blr
377entry:
378
379
380  %vecext = extractelement <16 x i8> %a, i32 0
381  %conv = sext i8 %vecext to i16
382  %vecinit = insertelement <8 x i16> undef, i16 %conv, i32 0
383  %vecext1 = extractelement <16 x i8> %a, i32 2
384  %conv2 = sext i8 %vecext1 to i16
385  %vecinit3 = insertelement <8 x i16> %vecinit, i16 %conv2, i32 1
386  %vecext4 = extractelement <16 x i8> %a, i32 4
387  %conv5 = sext i8 %vecext4 to i16
388  %vecinit6 = insertelement <8 x i16> %vecinit3, i16 %conv5, i32 2
389  %vecext7 = extractelement <16 x i8> %a, i32 6
390  %conv8 = sext i8 %vecext7 to i16
391  %vecinit9 = insertelement <8 x i16> %vecinit6, i16 %conv8, i32 3
392  %vecext10 = extractelement <16 x i8> %a, i32 8
393  %conv11 = sext i8 %vecext10 to i16
394  %vecinit12 = insertelement <8 x i16> %vecinit9, i16 %conv11, i32 4
395  %vecext13 = extractelement <16 x i8> %a, i32 10
396  %conv14 = sext i8 %vecext13 to i16
397  %vecinit15 = insertelement <8 x i16> %vecinit12, i16 %conv14, i32 5
398  %vecext16 = extractelement <16 x i8> %a, i32 12
399  %conv17 = sext i8 %vecext16 to i16
400  %vecinit18 = insertelement <8 x i16> %vecinit15, i16 %conv17, i32 6
401  %vecext19 = extractelement <16 x i8> %a, i32 14
402  %conv20 = sext i8 %vecext19 to i16
403  %vecinit21 = insertelement <8 x i16> %vecinit18, i16 %conv20, i32 7
404  ret <8 x i16> %vecinit21
405}
406