1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s --check-prefix=CHECK-P8 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s --check-prefix=CHECK-P9 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 10; RUN: FileCheck %s --check-prefix=CHECK-BE 11 12define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 { 13; CHECK-P8-LABEL: test2elt: 14; CHECK-P8: # %bb.0: # %entry 15; CHECK-P8-NEXT: mtfprd f0, r3 16; CHECK-P8-NEXT: xxswapd v2, vs0 17; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 18; CHECK-P8-NEXT: xvcvspdp vs0, vs0 19; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 20; CHECK-P8-NEXT: blr 21; 22; CHECK-P9-LABEL: test2elt: 23; CHECK-P9: # %bb.0: # %entry 24; CHECK-P9-NEXT: mtfprd f0, r3 25; CHECK-P9-NEXT: xxswapd v2, vs0 26; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 27; CHECK-P9-NEXT: xvcvspdp vs0, vs0 28; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 29; CHECK-P9-NEXT: blr 30; 31; CHECK-BE-LABEL: test2elt: 32; CHECK-BE: # %bb.0: # %entry 33; CHECK-BE-NEXT: mtfprd f0, r3 34; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0 35; CHECK-BE-NEXT: xvcvspdp vs0, vs0 36; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 37; CHECK-BE-NEXT: blr 38entry: 39 %0 = bitcast i64 %a.coerce to <2 x float> 40 %1 = fptoui <2 x float> %0 to <2 x i64> 41 ret <2 x i64> %1 42} 43 44define void @test4elt(ptr noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 { 45; CHECK-P8-LABEL: test4elt: 46; CHECK-P8: # %bb.0: # %entry 47; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 48; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 49; CHECK-P8-NEXT: li r4, 16 50; CHECK-P8-NEXT: xvcvspdp vs0, vs0 51; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 52; CHECK-P8-NEXT: xvcvspdp vs0, vs1 53; CHECK-P8-NEXT: xvcvdpuxds v3, vs0 54; CHECK-P8-NEXT: xxswapd vs1, v2 55; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 56; CHECK-P8-NEXT: xxswapd vs0, v3 57; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 58; CHECK-P8-NEXT: blr 59; 60; CHECK-P9-LABEL: test4elt: 61; CHECK-P9: # %bb.0: # %entry 62; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 63; CHECK-P9-NEXT: xxmrghw vs1, v2, v2 64; CHECK-P9-NEXT: xvcvspdp vs0, vs0 65; CHECK-P9-NEXT: xvcvspdp vs1, vs1 66; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 67; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 68; CHECK-P9-NEXT: stxv vs1, 16(r3) 69; CHECK-P9-NEXT: stxv vs0, 0(r3) 70; CHECK-P9-NEXT: blr 71; 72; CHECK-BE-LABEL: test4elt: 73; CHECK-BE: # %bb.0: # %entry 74; CHECK-BE-NEXT: xxmrghw vs0, v2, v2 75; CHECK-BE-NEXT: xxmrglw vs1, v2, v2 76; CHECK-BE-NEXT: xvcvspdp vs0, vs0 77; CHECK-BE-NEXT: xvcvspdp vs1, vs1 78; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 79; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 80; CHECK-BE-NEXT: stxv vs1, 16(r3) 81; CHECK-BE-NEXT: stxv vs0, 0(r3) 82; CHECK-BE-NEXT: blr 83entry: 84 %0 = fptoui <4 x float> %a to <4 x i64> 85 store <4 x i64> %0, ptr %agg.result, align 32 86 ret void 87} 88 89define void @test8elt(ptr noalias nocapture sret(<8 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 90; CHECK-P8-LABEL: test8elt: 91; CHECK-P8: # %bb.0: # %entry 92; CHECK-P8-NEXT: li r5, 16 93; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 94; CHECK-P8-NEXT: xxswapd v2, vs0 95; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 96; CHECK-P8-NEXT: li r4, 48 97; CHECK-P8-NEXT: xxmrglw vs1, v2, v2 98; CHECK-P8-NEXT: xvcvspdp vs1, vs1 99; CHECK-P8-NEXT: xxswapd v3, vs0 100; CHECK-P8-NEXT: xxmrghw vs0, v2, v2 101; CHECK-P8-NEXT: xvcvspdp vs0, vs0 102; CHECK-P8-NEXT: xvcvdpuxds v2, vs1 103; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 104; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 105; CHECK-P8-NEXT: xvcvspdp vs2, vs2 106; CHECK-P8-NEXT: xvcvspdp vs3, vs3 107; CHECK-P8-NEXT: xvcvdpuxds v3, vs0 108; CHECK-P8-NEXT: xvcvdpuxds v4, vs2 109; CHECK-P8-NEXT: xxswapd vs1, v2 110; CHECK-P8-NEXT: xxswapd vs0, v3 111; CHECK-P8-NEXT: xvcvdpuxds v3, vs3 112; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 113; CHECK-P8-NEXT: li r4, 32 114; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 115; CHECK-P8-NEXT: xxswapd vs3, v4 116; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 117; CHECK-P8-NEXT: xxswapd vs2, v3 118; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 119; CHECK-P8-NEXT: blr 120; 121; CHECK-P9-LABEL: test8elt: 122; CHECK-P9: # %bb.0: # %entry 123; CHECK-P9-NEXT: lxv vs0, 16(r4) 124; CHECK-P9-NEXT: lxv vs1, 0(r4) 125; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 126; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 127; CHECK-P9-NEXT: xxmrglw vs3, vs0, vs0 128; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 129; CHECK-P9-NEXT: xvcvspdp vs2, vs2 130; CHECK-P9-NEXT: xvcvspdp vs1, vs1 131; CHECK-P9-NEXT: xvcvspdp vs3, vs3 132; CHECK-P9-NEXT: xvcvspdp vs0, vs0 133; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 134; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 135; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 136; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 137; CHECK-P9-NEXT: stxv vs0, 48(r3) 138; CHECK-P9-NEXT: stxv vs3, 32(r3) 139; CHECK-P9-NEXT: stxv vs1, 16(r3) 140; CHECK-P9-NEXT: stxv vs2, 0(r3) 141; CHECK-P9-NEXT: blr 142; 143; CHECK-BE-LABEL: test8elt: 144; CHECK-BE: # %bb.0: # %entry 145; CHECK-BE-NEXT: lxv vs0, 16(r4) 146; CHECK-BE-NEXT: lxv vs1, 0(r4) 147; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 148; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 149; CHECK-BE-NEXT: xxmrghw vs3, vs0, vs0 150; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 151; CHECK-BE-NEXT: xvcvspdp vs2, vs2 152; CHECK-BE-NEXT: xvcvspdp vs1, vs1 153; CHECK-BE-NEXT: xvcvspdp vs3, vs3 154; CHECK-BE-NEXT: xvcvspdp vs0, vs0 155; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 156; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 157; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 158; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 159; CHECK-BE-NEXT: stxv vs0, 48(r3) 160; CHECK-BE-NEXT: stxv vs3, 32(r3) 161; CHECK-BE-NEXT: stxv vs1, 16(r3) 162; CHECK-BE-NEXT: stxv vs2, 0(r3) 163; CHECK-BE-NEXT: blr 164entry: 165 %a = load <8 x float>, ptr %0, align 32 166 %1 = fptoui <8 x float> %a to <8 x i64> 167 store <8 x i64> %1, ptr %agg.result, align 64 168 ret void 169} 170 171define void @test16elt(ptr noalias nocapture sret(<16 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 172; CHECK-P8-LABEL: test16elt: 173; CHECK-P8: # %bb.0: # %entry 174; CHECK-P8-NEXT: li r5, 48 175; CHECK-P8-NEXT: li r6, 32 176; CHECK-P8-NEXT: li r7, 16 177; CHECK-P8-NEXT: lxvd2x vs3, 0, r4 178; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 179; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 180; CHECK-P8-NEXT: lxvd2x vs2, r4, r7 181; CHECK-P8-NEXT: li r4, 112 182; CHECK-P8-NEXT: xxswapd v4, vs3 183; CHECK-P8-NEXT: xxswapd v2, vs0 184; CHECK-P8-NEXT: xxswapd v3, vs1 185; CHECK-P8-NEXT: xxmrglw vs6, v4, v4 186; CHECK-P8-NEXT: xxmrghw vs7, v4, v4 187; CHECK-P8-NEXT: xvcvspdp vs6, vs6 188; CHECK-P8-NEXT: xvcvspdp vs7, vs7 189; CHECK-P8-NEXT: xvcvdpuxds v1, vs7 190; CHECK-P8-NEXT: xxmrghw vs0, v2, v2 191; CHECK-P8-NEXT: xxmrglw vs1, v2, v2 192; CHECK-P8-NEXT: xvcvspdp vs1, vs1 193; CHECK-P8-NEXT: xvcvspdp vs0, vs0 194; CHECK-P8-NEXT: xxswapd v2, vs2 195; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 196; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 197; CHECK-P8-NEXT: xvcvspdp vs3, vs3 198; CHECK-P8-NEXT: xvcvspdp vs2, vs2 199; CHECK-P8-NEXT: xvcvdpuxds v4, vs0 200; CHECK-P8-NEXT: xvcvdpuxds v0, vs1 201; CHECK-P8-NEXT: xvcvdpuxds v5, vs3 202; CHECK-P8-NEXT: xxmrglw vs4, v2, v2 203; CHECK-P8-NEXT: xxmrghw vs5, v2, v2 204; CHECK-P8-NEXT: xvcvspdp vs4, vs4 205; CHECK-P8-NEXT: xvcvspdp vs5, vs5 206; CHECK-P8-NEXT: xvcvdpuxds v2, vs4 207; CHECK-P8-NEXT: xvcvdpuxds v3, vs5 208; CHECK-P8-NEXT: xxswapd vs4, v1 209; CHECK-P8-NEXT: stxvd2x vs4, r3, r7 210; CHECK-P8-NEXT: xxswapd vs0, v4 211; CHECK-P8-NEXT: xvcvdpuxds v4, vs2 212; CHECK-P8-NEXT: xxswapd vs1, v0 213; CHECK-P8-NEXT: xvcvdpuxds v0, vs6 214; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 215; CHECK-P8-NEXT: li r4, 96 216; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 217; CHECK-P8-NEXT: li r4, 80 218; CHECK-P8-NEXT: xxswapd vs0, v5 219; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 220; CHECK-P8-NEXT: li r4, 64 221; CHECK-P8-NEXT: xxswapd vs3, v2 222; CHECK-P8-NEXT: stxvd2x vs3, r3, r6 223; CHECK-P8-NEXT: xxswapd vs1, v3 224; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 225; CHECK-P8-NEXT: xxswapd vs2, v4 226; CHECK-P8-NEXT: xxswapd vs5, v0 227; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 228; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 229; CHECK-P8-NEXT: blr 230; 231; CHECK-P9-LABEL: test16elt: 232; CHECK-P9: # %bb.0: # %entry 233; CHECK-P9-NEXT: lxv vs0, 48(r4) 234; CHECK-P9-NEXT: lxv vs1, 0(r4) 235; CHECK-P9-NEXT: lxv vs3, 16(r4) 236; CHECK-P9-NEXT: lxv vs5, 32(r4) 237; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 238; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 239; CHECK-P9-NEXT: xxmrglw vs4, vs3, vs3 240; CHECK-P9-NEXT: xxmrghw vs3, vs3, vs3 241; CHECK-P9-NEXT: xxmrglw vs6, vs5, vs5 242; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5 243; CHECK-P9-NEXT: xxmrglw vs7, vs0, vs0 244; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 245; CHECK-P9-NEXT: xvcvspdp vs2, vs2 246; CHECK-P9-NEXT: xvcvspdp vs1, vs1 247; CHECK-P9-NEXT: xvcvspdp vs4, vs4 248; CHECK-P9-NEXT: xvcvspdp vs3, vs3 249; CHECK-P9-NEXT: xvcvspdp vs6, vs6 250; CHECK-P9-NEXT: xvcvspdp vs5, vs5 251; CHECK-P9-NEXT: xvcvspdp vs7, vs7 252; CHECK-P9-NEXT: xvcvspdp vs0, vs0 253; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 254; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 255; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4 256; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 257; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 258; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 259; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 260; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 261; CHECK-P9-NEXT: stxv vs0, 112(r3) 262; CHECK-P9-NEXT: stxv vs7, 96(r3) 263; CHECK-P9-NEXT: stxv vs5, 80(r3) 264; CHECK-P9-NEXT: stxv vs6, 64(r3) 265; CHECK-P9-NEXT: stxv vs3, 48(r3) 266; CHECK-P9-NEXT: stxv vs4, 32(r3) 267; CHECK-P9-NEXT: stxv vs1, 16(r3) 268; CHECK-P9-NEXT: stxv vs2, 0(r3) 269; CHECK-P9-NEXT: blr 270; 271; CHECK-BE-LABEL: test16elt: 272; CHECK-BE: # %bb.0: # %entry 273; CHECK-BE-NEXT: lxv vs0, 48(r4) 274; CHECK-BE-NEXT: lxv vs1, 0(r4) 275; CHECK-BE-NEXT: lxv vs3, 16(r4) 276; CHECK-BE-NEXT: lxv vs5, 32(r4) 277; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 278; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 279; CHECK-BE-NEXT: xxmrghw vs4, vs3, vs3 280; CHECK-BE-NEXT: xxmrglw vs3, vs3, vs3 281; CHECK-BE-NEXT: xxmrghw vs6, vs5, vs5 282; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5 283; CHECK-BE-NEXT: xxmrghw vs7, vs0, vs0 284; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 285; CHECK-BE-NEXT: xvcvspdp vs2, vs2 286; CHECK-BE-NEXT: xvcvspdp vs1, vs1 287; CHECK-BE-NEXT: xvcvspdp vs4, vs4 288; CHECK-BE-NEXT: xvcvspdp vs3, vs3 289; CHECK-BE-NEXT: xvcvspdp vs6, vs6 290; CHECK-BE-NEXT: xvcvspdp vs5, vs5 291; CHECK-BE-NEXT: xvcvspdp vs7, vs7 292; CHECK-BE-NEXT: xvcvspdp vs0, vs0 293; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 294; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 295; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4 296; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 297; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 298; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 299; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 300; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 301; CHECK-BE-NEXT: stxv vs0, 112(r3) 302; CHECK-BE-NEXT: stxv vs7, 96(r3) 303; CHECK-BE-NEXT: stxv vs5, 80(r3) 304; CHECK-BE-NEXT: stxv vs6, 64(r3) 305; CHECK-BE-NEXT: stxv vs3, 48(r3) 306; CHECK-BE-NEXT: stxv vs4, 32(r3) 307; CHECK-BE-NEXT: stxv vs1, 16(r3) 308; CHECK-BE-NEXT: stxv vs2, 0(r3) 309; CHECK-BE-NEXT: blr 310entry: 311 %a = load <16 x float>, ptr %0, align 64 312 %1 = fptoui <16 x float> %a to <16 x i64> 313 store <16 x i64> %1, ptr %agg.result, align 128 314 ret void 315} 316 317define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { 318; CHECK-P8-LABEL: test2elt_signed: 319; CHECK-P8: # %bb.0: # %entry 320; CHECK-P8-NEXT: mtfprd f0, r3 321; CHECK-P8-NEXT: xxswapd v2, vs0 322; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 323; CHECK-P8-NEXT: xvcvspdp vs0, vs0 324; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 325; CHECK-P8-NEXT: blr 326; 327; CHECK-P9-LABEL: test2elt_signed: 328; CHECK-P9: # %bb.0: # %entry 329; CHECK-P9-NEXT: mtfprd f0, r3 330; CHECK-P9-NEXT: xxswapd v2, vs0 331; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 332; CHECK-P9-NEXT: xvcvspdp vs0, vs0 333; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 334; CHECK-P9-NEXT: blr 335; 336; CHECK-BE-LABEL: test2elt_signed: 337; CHECK-BE: # %bb.0: # %entry 338; CHECK-BE-NEXT: mtfprd f0, r3 339; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0 340; CHECK-BE-NEXT: xvcvspdp vs0, vs0 341; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 342; CHECK-BE-NEXT: blr 343entry: 344 %0 = bitcast i64 %a.coerce to <2 x float> 345 %1 = fptoui <2 x float> %0 to <2 x i64> 346 ret <2 x i64> %1 347} 348 349define void @test4elt_signed(ptr noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 { 350; CHECK-P8-LABEL: test4elt_signed: 351; CHECK-P8: # %bb.0: # %entry 352; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 353; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 354; CHECK-P8-NEXT: li r4, 16 355; CHECK-P8-NEXT: xvcvspdp vs0, vs0 356; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 357; CHECK-P8-NEXT: xvcvspdp vs0, vs1 358; CHECK-P8-NEXT: xvcvdpuxds v3, vs0 359; CHECK-P8-NEXT: xxswapd vs1, v2 360; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 361; CHECK-P8-NEXT: xxswapd vs0, v3 362; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 363; CHECK-P8-NEXT: blr 364; 365; CHECK-P9-LABEL: test4elt_signed: 366; CHECK-P9: # %bb.0: # %entry 367; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 368; CHECK-P9-NEXT: xxmrghw vs1, v2, v2 369; CHECK-P9-NEXT: xvcvspdp vs0, vs0 370; CHECK-P9-NEXT: xvcvspdp vs1, vs1 371; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 372; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 373; CHECK-P9-NEXT: stxv vs1, 16(r3) 374; CHECK-P9-NEXT: stxv vs0, 0(r3) 375; CHECK-P9-NEXT: blr 376; 377; CHECK-BE-LABEL: test4elt_signed: 378; CHECK-BE: # %bb.0: # %entry 379; CHECK-BE-NEXT: xxmrghw vs0, v2, v2 380; CHECK-BE-NEXT: xxmrglw vs1, v2, v2 381; CHECK-BE-NEXT: xvcvspdp vs0, vs0 382; CHECK-BE-NEXT: xvcvspdp vs1, vs1 383; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 384; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 385; CHECK-BE-NEXT: stxv vs1, 16(r3) 386; CHECK-BE-NEXT: stxv vs0, 0(r3) 387; CHECK-BE-NEXT: blr 388entry: 389 %0 = fptoui <4 x float> %a to <4 x i64> 390 store <4 x i64> %0, ptr %agg.result, align 32 391 ret void 392} 393 394define void @test8elt_signed(ptr noalias nocapture sret(<8 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 395; CHECK-P8-LABEL: test8elt_signed: 396; CHECK-P8: # %bb.0: # %entry 397; CHECK-P8-NEXT: li r5, 16 398; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 399; CHECK-P8-NEXT: xxswapd v2, vs0 400; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 401; CHECK-P8-NEXT: li r4, 48 402; CHECK-P8-NEXT: xxmrglw vs1, v2, v2 403; CHECK-P8-NEXT: xvcvspdp vs1, vs1 404; CHECK-P8-NEXT: xxswapd v3, vs0 405; CHECK-P8-NEXT: xxmrghw vs0, v2, v2 406; CHECK-P8-NEXT: xvcvspdp vs0, vs0 407; CHECK-P8-NEXT: xvcvdpuxds v2, vs1 408; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 409; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 410; CHECK-P8-NEXT: xvcvspdp vs2, vs2 411; CHECK-P8-NEXT: xvcvspdp vs3, vs3 412; CHECK-P8-NEXT: xvcvdpuxds v3, vs0 413; CHECK-P8-NEXT: xvcvdpuxds v4, vs2 414; CHECK-P8-NEXT: xxswapd vs1, v2 415; CHECK-P8-NEXT: xxswapd vs0, v3 416; CHECK-P8-NEXT: xvcvdpuxds v3, vs3 417; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 418; CHECK-P8-NEXT: li r4, 32 419; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 420; CHECK-P8-NEXT: xxswapd vs3, v4 421; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 422; CHECK-P8-NEXT: xxswapd vs2, v3 423; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 424; CHECK-P8-NEXT: blr 425; 426; CHECK-P9-LABEL: test8elt_signed: 427; CHECK-P9: # %bb.0: # %entry 428; CHECK-P9-NEXT: lxv vs0, 16(r4) 429; CHECK-P9-NEXT: lxv vs1, 0(r4) 430; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 431; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 432; CHECK-P9-NEXT: xxmrglw vs3, vs0, vs0 433; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 434; CHECK-P9-NEXT: xvcvspdp vs2, vs2 435; CHECK-P9-NEXT: xvcvspdp vs1, vs1 436; CHECK-P9-NEXT: xvcvspdp vs3, vs3 437; CHECK-P9-NEXT: xvcvspdp vs0, vs0 438; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 439; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 440; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 441; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 442; CHECK-P9-NEXT: stxv vs0, 48(r3) 443; CHECK-P9-NEXT: stxv vs3, 32(r3) 444; CHECK-P9-NEXT: stxv vs1, 16(r3) 445; CHECK-P9-NEXT: stxv vs2, 0(r3) 446; CHECK-P9-NEXT: blr 447; 448; CHECK-BE-LABEL: test8elt_signed: 449; CHECK-BE: # %bb.0: # %entry 450; CHECK-BE-NEXT: lxv vs0, 16(r4) 451; CHECK-BE-NEXT: lxv vs1, 0(r4) 452; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 453; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 454; CHECK-BE-NEXT: xxmrghw vs3, vs0, vs0 455; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 456; CHECK-BE-NEXT: xvcvspdp vs2, vs2 457; CHECK-BE-NEXT: xvcvspdp vs1, vs1 458; CHECK-BE-NEXT: xvcvspdp vs3, vs3 459; CHECK-BE-NEXT: xvcvspdp vs0, vs0 460; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 461; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 462; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 463; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 464; CHECK-BE-NEXT: stxv vs0, 48(r3) 465; CHECK-BE-NEXT: stxv vs3, 32(r3) 466; CHECK-BE-NEXT: stxv vs1, 16(r3) 467; CHECK-BE-NEXT: stxv vs2, 0(r3) 468; CHECK-BE-NEXT: blr 469entry: 470 %a = load <8 x float>, ptr %0, align 32 471 %1 = fptoui <8 x float> %a to <8 x i64> 472 store <8 x i64> %1, ptr %agg.result, align 64 473 ret void 474} 475 476define void @test16elt_signed(ptr noalias nocapture sret(<16 x i64>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 477; CHECK-P8-LABEL: test16elt_signed: 478; CHECK-P8: # %bb.0: # %entry 479; CHECK-P8-NEXT: li r5, 48 480; CHECK-P8-NEXT: li r6, 32 481; CHECK-P8-NEXT: li r7, 16 482; CHECK-P8-NEXT: lxvd2x vs3, 0, r4 483; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 484; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 485; CHECK-P8-NEXT: lxvd2x vs2, r4, r7 486; CHECK-P8-NEXT: li r4, 112 487; CHECK-P8-NEXT: xxswapd v4, vs3 488; CHECK-P8-NEXT: xxswapd v2, vs0 489; CHECK-P8-NEXT: xxswapd v3, vs1 490; CHECK-P8-NEXT: xxmrglw vs6, v4, v4 491; CHECK-P8-NEXT: xxmrghw vs7, v4, v4 492; CHECK-P8-NEXT: xvcvspdp vs6, vs6 493; CHECK-P8-NEXT: xvcvspdp vs7, vs7 494; CHECK-P8-NEXT: xvcvdpuxds v1, vs7 495; CHECK-P8-NEXT: xxmrghw vs0, v2, v2 496; CHECK-P8-NEXT: xxmrglw vs1, v2, v2 497; CHECK-P8-NEXT: xvcvspdp vs1, vs1 498; CHECK-P8-NEXT: xvcvspdp vs0, vs0 499; CHECK-P8-NEXT: xxswapd v2, vs2 500; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 501; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 502; CHECK-P8-NEXT: xvcvspdp vs3, vs3 503; CHECK-P8-NEXT: xvcvspdp vs2, vs2 504; CHECK-P8-NEXT: xvcvdpuxds v4, vs0 505; CHECK-P8-NEXT: xvcvdpuxds v0, vs1 506; CHECK-P8-NEXT: xvcvdpuxds v5, vs3 507; CHECK-P8-NEXT: xxmrglw vs4, v2, v2 508; CHECK-P8-NEXT: xxmrghw vs5, v2, v2 509; CHECK-P8-NEXT: xvcvspdp vs4, vs4 510; CHECK-P8-NEXT: xvcvspdp vs5, vs5 511; CHECK-P8-NEXT: xvcvdpuxds v2, vs4 512; CHECK-P8-NEXT: xvcvdpuxds v3, vs5 513; CHECK-P8-NEXT: xxswapd vs4, v1 514; CHECK-P8-NEXT: stxvd2x vs4, r3, r7 515; CHECK-P8-NEXT: xxswapd vs0, v4 516; CHECK-P8-NEXT: xvcvdpuxds v4, vs2 517; CHECK-P8-NEXT: xxswapd vs1, v0 518; CHECK-P8-NEXT: xvcvdpuxds v0, vs6 519; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 520; CHECK-P8-NEXT: li r4, 96 521; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 522; CHECK-P8-NEXT: li r4, 80 523; CHECK-P8-NEXT: xxswapd vs0, v5 524; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 525; CHECK-P8-NEXT: li r4, 64 526; CHECK-P8-NEXT: xxswapd vs3, v2 527; CHECK-P8-NEXT: stxvd2x vs3, r3, r6 528; CHECK-P8-NEXT: xxswapd vs1, v3 529; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 530; CHECK-P8-NEXT: xxswapd vs2, v4 531; CHECK-P8-NEXT: xxswapd vs5, v0 532; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 533; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 534; CHECK-P8-NEXT: blr 535; 536; CHECK-P9-LABEL: test16elt_signed: 537; CHECK-P9: # %bb.0: # %entry 538; CHECK-P9-NEXT: lxv vs0, 48(r4) 539; CHECK-P9-NEXT: lxv vs1, 0(r4) 540; CHECK-P9-NEXT: lxv vs3, 16(r4) 541; CHECK-P9-NEXT: lxv vs5, 32(r4) 542; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 543; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 544; CHECK-P9-NEXT: xxmrglw vs4, vs3, vs3 545; CHECK-P9-NEXT: xxmrghw vs3, vs3, vs3 546; CHECK-P9-NEXT: xxmrglw vs6, vs5, vs5 547; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5 548; CHECK-P9-NEXT: xxmrglw vs7, vs0, vs0 549; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 550; CHECK-P9-NEXT: xvcvspdp vs2, vs2 551; CHECK-P9-NEXT: xvcvspdp vs1, vs1 552; CHECK-P9-NEXT: xvcvspdp vs4, vs4 553; CHECK-P9-NEXT: xvcvspdp vs3, vs3 554; CHECK-P9-NEXT: xvcvspdp vs6, vs6 555; CHECK-P9-NEXT: xvcvspdp vs5, vs5 556; CHECK-P9-NEXT: xvcvspdp vs7, vs7 557; CHECK-P9-NEXT: xvcvspdp vs0, vs0 558; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 559; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 560; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4 561; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 562; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 563; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 564; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 565; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 566; CHECK-P9-NEXT: stxv vs0, 112(r3) 567; CHECK-P9-NEXT: stxv vs7, 96(r3) 568; CHECK-P9-NEXT: stxv vs5, 80(r3) 569; CHECK-P9-NEXT: stxv vs6, 64(r3) 570; CHECK-P9-NEXT: stxv vs3, 48(r3) 571; CHECK-P9-NEXT: stxv vs4, 32(r3) 572; CHECK-P9-NEXT: stxv vs1, 16(r3) 573; CHECK-P9-NEXT: stxv vs2, 0(r3) 574; CHECK-P9-NEXT: blr 575; 576; CHECK-BE-LABEL: test16elt_signed: 577; CHECK-BE: # %bb.0: # %entry 578; CHECK-BE-NEXT: lxv vs0, 48(r4) 579; CHECK-BE-NEXT: lxv vs1, 0(r4) 580; CHECK-BE-NEXT: lxv vs3, 16(r4) 581; CHECK-BE-NEXT: lxv vs5, 32(r4) 582; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 583; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 584; CHECK-BE-NEXT: xxmrghw vs4, vs3, vs3 585; CHECK-BE-NEXT: xxmrglw vs3, vs3, vs3 586; CHECK-BE-NEXT: xxmrghw vs6, vs5, vs5 587; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5 588; CHECK-BE-NEXT: xxmrghw vs7, vs0, vs0 589; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 590; CHECK-BE-NEXT: xvcvspdp vs2, vs2 591; CHECK-BE-NEXT: xvcvspdp vs1, vs1 592; CHECK-BE-NEXT: xvcvspdp vs4, vs4 593; CHECK-BE-NEXT: xvcvspdp vs3, vs3 594; CHECK-BE-NEXT: xvcvspdp vs6, vs6 595; CHECK-BE-NEXT: xvcvspdp vs5, vs5 596; CHECK-BE-NEXT: xvcvspdp vs7, vs7 597; CHECK-BE-NEXT: xvcvspdp vs0, vs0 598; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 599; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 600; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4 601; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 602; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 603; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 604; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 605; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 606; CHECK-BE-NEXT: stxv vs0, 112(r3) 607; CHECK-BE-NEXT: stxv vs7, 96(r3) 608; CHECK-BE-NEXT: stxv vs5, 80(r3) 609; CHECK-BE-NEXT: stxv vs6, 64(r3) 610; CHECK-BE-NEXT: stxv vs3, 48(r3) 611; CHECK-BE-NEXT: stxv vs4, 32(r3) 612; CHECK-BE-NEXT: stxv vs1, 16(r3) 613; CHECK-BE-NEXT: stxv vs2, 0(r3) 614; CHECK-BE-NEXT: blr 615entry: 616 %a = load <16 x float>, ptr %0, align 64 617 %1 = fptoui <16 x float> %a to <16 x i64> 618 store <16 x i64> %1, ptr %agg.result, align 128 619 ret void 620} 621