1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Test the doubleword comparison expansions on Power7 3; 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 5; RUN: -mcpu=pwr7 < %s | FileCheck %s 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 7; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE 8 9define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone { 10; CHECK-LABEL: v2si64_cmp: 11; CHECK: # %bb.0: 12; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha 13; CHECK-NEXT: vcmpequw 2, 2, 3 14; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l 15; CHECK-NEXT: lxvd2x 0, 0, 3 16; CHECK-NEXT: xxswapd 36, 0 17; CHECK-NEXT: vperm 3, 2, 2, 4 18; CHECK-NEXT: xxland 34, 35, 34 19; CHECK-NEXT: blr 20; 21; CHECK-BE-LABEL: v2si64_cmp: 22; CHECK-BE: # %bb.0: 23; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha 24; CHECK-BE-NEXT: vcmpequw 2, 2, 3 25; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l 26; CHECK-BE-NEXT: lxvw4x 35, 0, 3 27; CHECK-BE-NEXT: vperm 3, 2, 2, 3 28; CHECK-BE-NEXT: xxland 34, 35, 34 29; CHECK-BE-NEXT: blr 30 %cmp = icmp eq <2 x i64> %x, %y 31 %result = sext <2 x i1> %cmp to <2 x i64> 32 ret <2 x i64> %result 33} 34 35; Greater than signed 36define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone { 37; CHECK-LABEL: v2si64_cmp_gt: 38; CHECK: # %bb.0: 39; CHECK-NEXT: xxswapd 0, 35 40; CHECK-NEXT: addi 3, 1, -32 41; CHECK-NEXT: xxswapd 1, 34 42; CHECK-NEXT: stxvd2x 0, 0, 3 43; CHECK-NEXT: addi 3, 1, -48 44; CHECK-NEXT: stxvd2x 1, 0, 3 45; CHECK-NEXT: ld 3, -24(1) 46; CHECK-NEXT: ld 4, -40(1) 47; CHECK-NEXT: ld 6, -48(1) 48; CHECK-NEXT: cmpd 4, 3 49; CHECK-NEXT: li 3, 0 50; CHECK-NEXT: li 4, -1 51; CHECK-NEXT: iselgt 5, 4, 3 52; CHECK-NEXT: std 5, -8(1) 53; CHECK-NEXT: ld 5, -32(1) 54; CHECK-NEXT: cmpd 6, 5 55; CHECK-NEXT: iselgt 3, 4, 3 56; CHECK-NEXT: std 3, -16(1) 57; CHECK-NEXT: addi 3, 1, -16 58; CHECK-NEXT: lxvd2x 0, 0, 3 59; CHECK-NEXT: xxswapd 34, 0 60; CHECK-NEXT: blr 61; 62; CHECK-BE-LABEL: v2si64_cmp_gt: 63; CHECK-BE: # %bb.0: 64; CHECK-BE-NEXT: addi 3, 1, -32 65; CHECK-BE-NEXT: stxvd2x 35, 0, 3 66; CHECK-BE-NEXT: addi 3, 1, -48 67; CHECK-BE-NEXT: stxvd2x 34, 0, 3 68; CHECK-BE-NEXT: ld 3, -24(1) 69; CHECK-BE-NEXT: ld 4, -40(1) 70; CHECK-BE-NEXT: ld 6, -48(1) 71; CHECK-BE-NEXT: cmpd 4, 3 72; CHECK-BE-NEXT: li 3, 0 73; CHECK-BE-NEXT: li 4, -1 74; CHECK-BE-NEXT: iselgt 5, 4, 3 75; CHECK-BE-NEXT: std 5, -8(1) 76; CHECK-BE-NEXT: ld 5, -32(1) 77; CHECK-BE-NEXT: cmpd 6, 5 78; CHECK-BE-NEXT: iselgt 3, 4, 3 79; CHECK-BE-NEXT: std 3, -16(1) 80; CHECK-BE-NEXT: addi 3, 1, -16 81; CHECK-BE-NEXT: lxvd2x 34, 0, 3 82; CHECK-BE-NEXT: blr 83 %cmp = icmp sgt <2 x i64> %x, %y 84 %result = sext <2 x i1> %cmp to <2 x i64> 85 ret <2 x i64> %result 86} 87 88; Greater than unsigned 89define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone { 90; CHECK-LABEL: v2ui64_cmp_gt: 91; CHECK: # %bb.0: 92; CHECK-NEXT: xxswapd 0, 35 93; CHECK-NEXT: addi 3, 1, -32 94; CHECK-NEXT: xxswapd 1, 34 95; CHECK-NEXT: stxvd2x 0, 0, 3 96; CHECK-NEXT: addi 3, 1, -48 97; CHECK-NEXT: stxvd2x 1, 0, 3 98; CHECK-NEXT: ld 3, -24(1) 99; CHECK-NEXT: ld 4, -40(1) 100; CHECK-NEXT: ld 6, -48(1) 101; CHECK-NEXT: cmpld 4, 3 102; CHECK-NEXT: li 3, 0 103; CHECK-NEXT: li 4, -1 104; CHECK-NEXT: iselgt 5, 4, 3 105; CHECK-NEXT: std 5, -8(1) 106; CHECK-NEXT: ld 5, -32(1) 107; CHECK-NEXT: cmpld 6, 5 108; CHECK-NEXT: iselgt 3, 4, 3 109; CHECK-NEXT: std 3, -16(1) 110; CHECK-NEXT: addi 3, 1, -16 111; CHECK-NEXT: lxvd2x 0, 0, 3 112; CHECK-NEXT: xxswapd 34, 0 113; CHECK-NEXT: blr 114; 115; CHECK-BE-LABEL: v2ui64_cmp_gt: 116; CHECK-BE: # %bb.0: 117; CHECK-BE-NEXT: addi 3, 1, -32 118; CHECK-BE-NEXT: stxvd2x 35, 0, 3 119; CHECK-BE-NEXT: addi 3, 1, -48 120; CHECK-BE-NEXT: stxvd2x 34, 0, 3 121; CHECK-BE-NEXT: ld 3, -24(1) 122; CHECK-BE-NEXT: ld 4, -40(1) 123; CHECK-BE-NEXT: ld 6, -48(1) 124; CHECK-BE-NEXT: cmpld 4, 3 125; CHECK-BE-NEXT: li 3, 0 126; CHECK-BE-NEXT: li 4, -1 127; CHECK-BE-NEXT: iselgt 5, 4, 3 128; CHECK-BE-NEXT: std 5, -8(1) 129; CHECK-BE-NEXT: ld 5, -32(1) 130; CHECK-BE-NEXT: cmpld 6, 5 131; CHECK-BE-NEXT: iselgt 3, 4, 3 132; CHECK-BE-NEXT: std 3, -16(1) 133; CHECK-BE-NEXT: addi 3, 1, -16 134; CHECK-BE-NEXT: lxvd2x 34, 0, 3 135; CHECK-BE-NEXT: blr 136 %cmp = icmp ugt <2 x i64> %x, %y 137 %result = sext <2 x i1> %cmp to <2 x i64> 138 ret <2 x i64> %result 139} 140 141; Check the intrinsics also 142declare i32 @llvm.ppc.altivec.vcmpequd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone 143declare i32 @llvm.ppc.altivec.vcmpgtsd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone 144declare i32 @llvm.ppc.altivec.vcmpgtud.p(i32, <2 x i64>, <2 x i64>) nounwind readnone 145 146define i32 @test_vcmpequd_p(<2 x i64> %x, <2 x i64> %y) { 147; CHECK-LABEL: test_vcmpequd_p: 148; CHECK: # %bb.0: 149; CHECK-NEXT: vcmpequw 2, 2, 3 150; CHECK-NEXT: xxlxor 35, 35, 35 151; CHECK-NEXT: xxsldwi 0, 34, 34, 1 152; CHECK-NEXT: xxland 0, 0, 34 153; CHECK-NEXT: xxspltw 1, 0, 2 154; CHECK-NEXT: xxspltw 0, 0, 0 155; CHECK-NEXT: xxmrghd 34, 0, 1 156; CHECK-NEXT: vcmpgtub. 2, 2, 3 157; CHECK-NEXT: mfocrf 3, 2 158; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 159; CHECK-NEXT: blr 160; 161; CHECK-BE-LABEL: test_vcmpequd_p: 162; CHECK-BE: # %bb.0: 163; CHECK-BE-NEXT: vcmpequw 2, 2, 3 164; CHECK-BE-NEXT: xxlxor 35, 35, 35 165; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 1 166; CHECK-BE-NEXT: xxland 0, 0, 34 167; CHECK-BE-NEXT: xxspltw 1, 0, 2 168; CHECK-BE-NEXT: xxspltw 0, 0, 0 169; CHECK-BE-NEXT: xxmrghd 34, 0, 1 170; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3 171; CHECK-BE-NEXT: mfocrf 3, 2 172; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31 173; CHECK-BE-NEXT: blr 174 %tmp = tail call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> %x, <2 x i64> %y) 175 ret i32 %tmp 176} 177 178define i32 @test_vcmpgtsd_p(<2 x i64> %x, <2 x i64> %y) { 179; CHECK-LABEL: test_vcmpgtsd_p: 180; CHECK: # %bb.0: 181; CHECK-NEXT: vcmpgtuw 4, 2, 3 182; CHECK-NEXT: xxsldwi 0, 36, 36, 1 183; CHECK-NEXT: vcmpequw 4, 2, 3 184; CHECK-NEXT: vcmpgtsw 2, 2, 3 185; CHECK-NEXT: xxlxor 35, 35, 35 186; CHECK-NEXT: xxland 0, 0, 36 187; CHECK-NEXT: xxlor 0, 34, 0 188; CHECK-NEXT: xxspltw 1, 0, 2 189; CHECK-NEXT: xxspltw 0, 0, 0 190; CHECK-NEXT: xxmrghd 34, 0, 1 191; CHECK-NEXT: vcmpgtub. 2, 2, 3 192; CHECK-NEXT: mfocrf 3, 2 193; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 194; CHECK-NEXT: blr 195; 196; CHECK-BE-LABEL: test_vcmpgtsd_p: 197; CHECK-BE: # %bb.0: 198; CHECK-BE-NEXT: vcmpgtuw 4, 2, 3 199; CHECK-BE-NEXT: xxsldwi 0, 36, 36, 1 200; CHECK-BE-NEXT: vcmpequw 4, 2, 3 201; CHECK-BE-NEXT: vcmpgtsw 2, 2, 3 202; CHECK-BE-NEXT: xxlxor 35, 35, 35 203; CHECK-BE-NEXT: xxland 0, 0, 36 204; CHECK-BE-NEXT: xxlor 0, 34, 0 205; CHECK-BE-NEXT: xxspltw 1, 0, 2 206; CHECK-BE-NEXT: xxspltw 0, 0, 0 207; CHECK-BE-NEXT: xxmrghd 34, 0, 1 208; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3 209; CHECK-BE-NEXT: mfocrf 3, 2 210; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31 211; CHECK-BE-NEXT: blr 212 %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsd.p(i32 2, <2 x i64> %x, <2 x i64> %y) 213 ret i32 %tmp 214} 215 216define i32 @test_vcmpgtud_p(<2 x i64> %x, <2 x i64> %y) { 217; CHECK-LABEL: test_vcmpgtud_p: 218; CHECK: # %bb.0: 219; CHECK-NEXT: vcmpgtuw 4, 2, 3 220; CHECK-NEXT: vcmpequw 2, 2, 3 221; CHECK-NEXT: xxlxor 35, 35, 35 222; CHECK-NEXT: xxsldwi 0, 36, 36, 1 223; CHECK-NEXT: xxland 0, 0, 34 224; CHECK-NEXT: xxlor 0, 36, 0 225; CHECK-NEXT: xxspltw 1, 0, 2 226; CHECK-NEXT: xxspltw 0, 0, 0 227; CHECK-NEXT: xxmrghd 34, 0, 1 228; CHECK-NEXT: vcmpgtub. 2, 2, 3 229; CHECK-NEXT: mfocrf 3, 2 230; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 231; CHECK-NEXT: blr 232; 233; CHECK-BE-LABEL: test_vcmpgtud_p: 234; CHECK-BE: # %bb.0: 235; CHECK-BE-NEXT: vcmpgtuw 4, 2, 3 236; CHECK-BE-NEXT: vcmpequw 2, 2, 3 237; CHECK-BE-NEXT: xxlxor 35, 35, 35 238; CHECK-BE-NEXT: xxsldwi 0, 36, 36, 1 239; CHECK-BE-NEXT: xxland 0, 0, 34 240; CHECK-BE-NEXT: xxlor 0, 36, 0 241; CHECK-BE-NEXT: xxspltw 1, 0, 2 242; CHECK-BE-NEXT: xxspltw 0, 0, 0 243; CHECK-BE-NEXT: xxmrghd 34, 0, 1 244; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3 245; CHECK-BE-NEXT: mfocrf 3, 2 246; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31 247; CHECK-BE-NEXT: blr 248 %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtud.p(i32 2, <2 x i64> %x, <2 x i64> %y) 249 ret i32 %tmp 250} 251