1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -mcpu=pwr9 < %s | FileCheck %s 3 4; Widen to <16 x i8> 5define <12 x i8> @zext_abdu(<12 x i8> %a, <12 x i8> %b) { 6; CHECK-LABEL: zext_abdu: 7; CHECK: # %bb.0: # %entry 8; CHECK-NEXT: vabsdub 2, 2, 3 9; CHECK-NEXT: blr 10entry: 11 %aa = zext <12 x i8> %a to <12 x i32> 12 %bb = zext <12 x i8> %b to <12 x i32> 13 %s = sub nsw <12 x i32> %aa, %bb 14 %c = icmp slt <12 x i32> %s, zeroinitializer 15 %ss = sub nsw <12 x i32> zeroinitializer, %s 16 %sel = select <12 x i1> %c, <12 x i32> %ss, <12 x i32> %s 17 %ret = trunc <12 x i32> %sel to <12 x i8> 18 ret <12 x i8> %ret 19} 20