xref: /llvm-project/llvm/test/CodeGen/PowerPC/umulfixsat.ll (revision d1924f0474b65fe3189ffd658a12f452e4696c28)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ppc32 | FileCheck %s
3
4declare  i32 @llvm.umul.fix.sat.i32(i32, i32, i32)
5
6define i32 @func1(i32 %x, i32 %y) nounwind {
7; CHECK-LABEL: func1:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    mulhwu. 5, 3, 4
10; CHECK-NEXT:    li 5, -1
11; CHECK-NEXT:    bne 0, .LBB0_2
12; CHECK-NEXT:  # %bb.1:
13; CHECK-NEXT:    mullw 5, 3, 4
14; CHECK-NEXT:  .LBB0_2:
15; CHECK-NEXT:    mr 3, 5
16; CHECK-NEXT:    blr
17  %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 0)
18  ret i32 %tmp
19}
20
21define i32 @func2(i32 %x, i32 %y) nounwind {
22; CHECK-LABEL: func2:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    mulhwu 6, 3, 4
25; CHECK-NEXT:    mr 5, 3
26; CHECK-NEXT:    cmplwi 6, 1
27; CHECK-NEXT:    li 3, -1
28; CHECK-NEXT:    bgtlr 0
29; CHECK-NEXT:  # %bb.1:
30; CHECK-NEXT:    mullw 3, 5, 4
31; CHECK-NEXT:    rotlwi 3, 3, 31
32; CHECK-NEXT:    rlwimi 3, 6, 31, 0, 0
33; CHECK-NEXT:    blr
34  %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 1)
35  ret i32 %tmp
36}
37