xref: /llvm-project/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll (revision b922a3621116b404d868af8b74cab25ab78555be)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
4; RUN:   -check-prefix=P9BE
5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck  %s \
7; RUN:   -check-prefix=P9LE
8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
10; RUN:   -check-prefix=P8BE
11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck  %s \
13; RUN:   -check-prefix=P8LE
14define dso_local <2 x double> @test1(<8 x i16> %a) {
15; P9BE-LABEL: test1:
16; P9BE:       # %bb.0: # %entry
17; P9BE-NEXT:    vextractuh v3, v2, 0
18; P9BE-NEXT:    vextractuh v2, v2, 2
19; P9BE-NEXT:    xscvuxddp f0, v3
20; P9BE-NEXT:    xscvuxddp f1, v2
21; P9BE-NEXT:    xxmrghd v2, vs0, vs1
22; P9BE-NEXT:    blr
23;
24; P9LE-LABEL: test1:
25; P9LE:       # %bb.0: # %entry
26; P9LE-NEXT:    vextractuh v3, v2, 14
27; P9LE-NEXT:    vextractuh v2, v2, 12
28; P9LE-NEXT:    xscvuxddp f0, v3
29; P9LE-NEXT:    xscvuxddp f1, v2
30; P9LE-NEXT:    xxmrghd v2, vs1, vs0
31; P9LE-NEXT:    blr
32;
33; P8BE-LABEL: test1:
34; P8BE:       # %bb.0: # %entry
35; P8BE-NEXT:    mfvsrd r3, v2
36; P8BE-NEXT:    rldicl r4, r3, 16, 48
37; P8BE-NEXT:    rldicl r3, r3, 32, 48
38; P8BE-NEXT:    clrlwi r4, r4, 16
39; P8BE-NEXT:    clrlwi r3, r3, 16
40; P8BE-NEXT:    mtfprwz f0, r4
41; P8BE-NEXT:    mtfprwz f1, r3
42; P8BE-NEXT:    xscvuxddp f0, f0
43; P8BE-NEXT:    xscvuxddp f1, f1
44; P8BE-NEXT:    xxmrghd v2, vs0, vs1
45; P8BE-NEXT:    blr
46;
47; P8LE-LABEL: test1:
48; P8LE:       # %bb.0: # %entry
49; P8LE-NEXT:    xxswapd vs0, v2
50; P8LE-NEXT:    mffprd r3, f0
51; P8LE-NEXT:    clrldi r4, r3, 48
52; P8LE-NEXT:    rldicl r3, r3, 48, 48
53; P8LE-NEXT:    clrlwi r4, r4, 16
54; P8LE-NEXT:    clrlwi r3, r3, 16
55; P8LE-NEXT:    mtfprwz f0, r4
56; P8LE-NEXT:    mtfprwz f1, r3
57; P8LE-NEXT:    xscvuxddp f0, f0
58; P8LE-NEXT:    xscvuxddp f1, f1
59; P8LE-NEXT:    xxmrghd v2, vs1, vs0
60; P8LE-NEXT:    blr
61entry:
62  %vecext = extractelement <8 x i16> %a, i32 0
63  %conv = uitofp i16 %vecext to double
64  %vecinit = insertelement <2 x double> undef, double %conv, i32 0
65  %vecext1 = extractelement <8 x i16> %a, i32 1
66  %conv2 = uitofp i16 %vecext1 to double
67  %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
68  ret <2 x double> %vecinit3
69}
70
71define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
72; P9BE-LABEL: test2:
73; P9BE:       # %bb.0: # %entry
74; P9BE-NEXT:    xxextractuw f0, v2, 0
75; P9BE-NEXT:    xxextractuw f1, v3, 4
76; P9BE-NEXT:    xscvuxddp f0, f0
77; P9BE-NEXT:    xscvuxddp f1, f1
78; P9BE-NEXT:    xxmrghd v2, vs0, vs1
79; P9BE-NEXT:    blr
80;
81; P9LE-LABEL: test2:
82; P9LE:       # %bb.0: # %entry
83; P9LE-NEXT:    xxextractuw f0, v2, 12
84; P9LE-NEXT:    xxextractuw f1, v3, 8
85; P9LE-NEXT:    xscvuxddp f0, f0
86; P9LE-NEXT:    xscvuxddp f1, f1
87; P9LE-NEXT:    xxmrghd v2, vs1, vs0
88; P9LE-NEXT:    blr
89;
90; P8BE-LABEL: test2:
91; P8BE:       # %bb.0: # %entry
92; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
93; P8BE-NEXT:    mffprwz r3, f0
94; P8BE-NEXT:    mtfprwz f0, r3
95; P8BE-NEXT:    mfvsrwz r3, v3
96; P8BE-NEXT:    mtfprwz f1, r3
97; P8BE-NEXT:    xscvuxddp f0, f0
98; P8BE-NEXT:    xscvuxddp f1, f1
99; P8BE-NEXT:    xxmrghd v2, vs0, vs1
100; P8BE-NEXT:    blr
101;
102; P8LE-LABEL: test2:
103; P8LE:       # %bb.0: # %entry
104; P8LE-NEXT:    xxswapd vs0, v2
105; P8LE-NEXT:    xxsldwi vs1, v3, v3, 1
106; P8LE-NEXT:    mffprwz r3, f0
107; P8LE-NEXT:    mtfprwz f0, r3
108; P8LE-NEXT:    mffprwz r3, f1
109; P8LE-NEXT:    mtfprwz f1, r3
110; P8LE-NEXT:    xscvuxddp f0, f0
111; P8LE-NEXT:    xscvuxddp f1, f1
112; P8LE-NEXT:    xxmrghd v2, vs1, vs0
113; P8LE-NEXT:    blr
114entry:
115  %vecext = extractelement <4 x i32> %a, i32 0
116  %conv = uitofp i32 %vecext to double
117  %vecinit = insertelement <2 x double> undef, double %conv, i32 0
118  %vecext1 = extractelement <4 x i32> %b, i32 1
119  %conv2 = uitofp i32 %vecext1 to double
120  %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
121  ret <2 x double> %vecinit3
122}
123