xref: /llvm-project/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll (revision b922a3621116b404d868af8b74cab25ab78555be)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8
9@glob = local_unnamed_addr global i64 0, align 8
10
11; Function Attrs: norecurse nounwind readnone
12define i64 @test_llgtsll(i64 %a, i64 %b) {
13; CHECK-LABEL: test_llgtsll:
14; CHECK:       # %bb.0: # %entry
15; CHECK-NEXT:    sradi r5, r4, 63
16; CHECK-NEXT:    rldicl r6, r3, 1, 63
17; CHECK-NEXT:    subc r3, r4, r3
18; CHECK-NEXT:    adde r3, r6, r5
19; CHECK-NEXT:    xori r3, r3, 1
20; CHECK-NEXT:    blr
21entry:
22  %cmp = icmp sgt i64 %a, %b
23  %conv1 = zext i1 %cmp to i64
24  ret i64 %conv1
25}
26
27; Function Attrs: norecurse nounwind readnone
28define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
29; CHECK-LABEL: test_llgtsll_sext:
30; CHECK:       # %bb.0: # %entry
31; CHECK-NEXT:    sradi r5, r4, 63
32; CHECK-NEXT:    rldicl r6, r3, 1, 63
33; CHECK-NEXT:    subc r3, r4, r3
34; CHECK-NEXT:    adde r3, r6, r5
35; CHECK-NEXT:    xori r3, r3, 1
36; CHECK-NEXT:    neg r3, r3
37; CHECK-NEXT:    blr
38entry:
39  %cmp = icmp sgt i64 %a, %b
40  %conv1 = sext i1 %cmp to i64
41  ret i64 %conv1
42}
43
44; FIXME
45; Function Attrs: norecurse nounwind readnone
46define i64 @test_llgtsll_z(i64 %a) {
47; CHECK-LABEL: test_llgtsll_z:
48; CHECK:       # %bb.0: # %entry
49; CHECK-NEXT:    addi r4, r3, -1
50; CHECK-NEXT:    nor r3, r4, r3
51; CHECK-NEXT:    rldicl r3, r3, 1, 63
52; CHECK-NEXT:    blr
53entry:
54  %cmp = icmp sgt i64 %a, 0
55  %conv1 = zext i1 %cmp to i64
56  ret i64 %conv1
57}
58
59; Function Attrs: norecurse nounwind readnone
60define i64 @test_llgtsll_sext_z(i64 %a) {
61; CHECK-LABEL: test_llgtsll_sext_z:
62; CHECK:       # %bb.0: # %entry
63; CHECK-NEXT:    addi r4, r3, -1
64; CHECK-NEXT:    nor r3, r4, r3
65; CHECK-NEXT:    sradi r3, r3, 63
66; CHECK-NEXT:    blr
67entry:
68  %cmp = icmp sgt i64 %a, 0
69  %conv1 = sext i1 %cmp to i64
70  ret i64 %conv1
71}
72
73; Function Attrs: norecurse nounwind
74define void @test_llgtsll_store(i64 %a, i64 %b) {
75; CHECK-LABEL: test_llgtsll_store:
76; CHECK:       # %bb.0: # %entry
77; CHECK-NEXT:    sradi r5, r4, 63
78; CHECK-NEXT:    rldicl r6, r3, 1, 63
79; CHECK-NEXT:    subc r3, r4, r3
80; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
81; CHECK-NEXT:    adde r3, r6, r5
82; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
83; CHECK-NEXT:    xori r3, r3, 1
84; CHECK-NEXT:    std r3, 0(r4)
85; CHECK-NEXT:    blr
86entry:
87  %cmp = icmp sgt i64 %a, %b
88  %conv1 = zext i1 %cmp to i64
89  store i64 %conv1, ptr @glob, align 8
90  ret void
91}
92
93; Function Attrs: norecurse nounwind
94define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
95; CHECK-LABEL: test_llgtsll_sext_store:
96; CHECK:       # %bb.0: # %entry
97; CHECK-NEXT:    sradi r5, r4, 63
98; CHECK-NEXT:    rldicl r6, r3, 1, 63
99; CHECK-NEXT:    subc r3, r4, r3
100; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
101; CHECK-NEXT:    adde r3, r6, r5
102; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
103; CHECK-NEXT:    xori r3, r3, 1
104; CHECK-NEXT:    neg r3, r3
105; CHECK-NEXT:    std r3, 0(r4)
106; CHECK-NEXT:    blr
107entry:
108  %cmp = icmp sgt i64 %a, %b
109  %conv1 = sext i1 %cmp to i64
110  store i64 %conv1, ptr @glob, align 8
111  ret void
112}
113
114; FIXME
115; Function Attrs: norecurse nounwind
116define void @test_llgtsll_z_store(i64 %a) {
117; CHECK-LABEL: test_llgtsll_z_store:
118; CHECK:       # %bb.0: # %entry
119; CHECK-NEXT:    addi r4, r3, -1
120; CHECK-NEXT:    nor r3, r4, r3
121; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
122; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
123; CHECK-NEXT:    rldicl r3, r3, 1, 63
124; CHECK-NEXT:    std r3, 0(r4)
125; CHECK-NEXT:    blr
126entry:
127  %cmp = icmp sgt i64 %a, 0
128  %conv1 = zext i1 %cmp to i64
129  store i64 %conv1, ptr @glob, align 8
130  ret void
131}
132
133; Function Attrs: norecurse nounwind
134define void @test_llgtsll_sext_z_store(i64 %a) {
135; CHECK-LABEL: test_llgtsll_sext_z_store:
136; CHECK:       # %bb.0: # %entry
137; CHECK-NEXT:    addi r4, r3, -1
138; CHECK-NEXT:    nor r3, r4, r3
139; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
140; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
141; CHECK-NEXT:    sradi r3, r3, 63
142; CHECK-NEXT:    std r3, 0(r4)
143; CHECK-NEXT:    blr
144entry:
145  %cmp = icmp sgt i64 %a, 0
146  %conv1 = sext i1 %cmp to i64
147  store i64 %conv1, ptr @glob, align 8
148  ret void
149}
150