xref: /llvm-project/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll (revision 8e901c255df45e38cb1d69a576804029e20868bf)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gep-opt=0 < %s | FileCheck %s
3; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-isel -ppc-gep-opt=0 < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
4target datalayout = "E-m:e-i64:64-n32:64"
5target triple = "powerpc64-unknown-linux-gnu"
6
7; Function Attrs: nounwind
8define void @jbd2_journal_commit_transaction(i32 %input1, ptr %input2, ptr %input3, ptr %input4) #0 {
9; CHECK-LABEL: jbd2_journal_commit_transaction:
10; CHECK:       # %bb.0: # %entry
11; CHECK-NEXT:    addi 7, 3, 1
12; CHECK-NEXT:    cmplwi 1, 3, 0
13; CHECK-NEXT:    li 8, -5
14; CHECK-NEXT:    lis 9, 4
15; CHECK-NEXT:    cmpld 6, 4, 5
16; CHECK-NEXT:    .p2align 4
17; CHECK-NEXT:  .LBB0_1: # %while.body392
18; CHECK-NEXT:    #
19; CHECK-NEXT:    bne- 1, .LBB0_4
20; CHECK-NEXT:  # %bb.2: # %wait_on_buffer.exit1319
21; CHECK-NEXT:    #
22; CHECK-NEXT:    ld 4, 0(6)
23; CHECK-NEXT:    mr 5, 4
24; CHECK-NEXT:    ldu 10, -72(5)
25; CHECK-NEXT:    andi. 10, 10, 1
26; CHECK-NEXT:    crmove 20, 1
27; CHECK-NEXT:    #APP
28; CHECK-NEXT:  .Ltmp0:
29; CHECK-NEXT:    .long 2101356712
30; CHECK-NEXT:    andc 10, 10, 9
31; CHECK-NEXT:    stdcx. 10, 0, 5
32; CHECK-NEXT:    bne- 0, .Ltmp0
33; CHECK-EMPTY:
34; CHECK-NEXT:    #NO_APP
35; CHECK-NEXT:    std 4, 0(6)
36; CHECK-NEXT:    bne+ 6, .LBB0_1
37; CHECK-NEXT:  # %bb.3:
38; CHECK-NEXT:    isel 7, 3, 8, 20
39; CHECK-NEXT:  .LBB0_4: # %while.end418
40; CHECK-NEXT:    cmplwi 7, 0
41; CHECK-NEXT:    beq 0, .LBB0_6
42; CHECK-NEXT:  # %bb.5: # %if.then420
43; CHECK-NEXT:  .LBB0_6: # %if.end421
44;
45; CHECK-NO-ISEL-LABEL: jbd2_journal_commit_transaction:
46; CHECK-NO-ISEL:       # %bb.0: # %entry
47; CHECK-NO-ISEL-NEXT:    addi 7, 3, 1
48; CHECK-NO-ISEL-NEXT:    cmplwi 1, 3, 0
49; CHECK-NO-ISEL-NEXT:    lis 8, 4
50; CHECK-NO-ISEL-NEXT:    cmpld 5, 4, 5
51; CHECK-NO-ISEL-NEXT:    b .LBB0_2
52; CHECK-NO-ISEL-NEXT:    .p2align 4
53; CHECK-NO-ISEL-NEXT:  .LBB0_1: # %wait_on_buffer.exit1319
54; CHECK-NO-ISEL-NEXT:    #
55; CHECK-NO-ISEL-NEXT:    #APP
56; CHECK-NO-ISEL-NEXT:  .Ltmp0:
57; CHECK-NO-ISEL-NEXT:    .long 2101364904
58; CHECK-NO-ISEL-NEXT:    andc 10, 10, 8
59; CHECK-NO-ISEL-NEXT:    stdcx. 10, 0, 9
60; CHECK-NO-ISEL-NEXT:    bne- 0, .Ltmp0
61; CHECK-NO-ISEL-EMPTY:
62; CHECK-NO-ISEL-NEXT:    #NO_APP
63; CHECK-NO-ISEL-NEXT:    std 5, 0(6)
64; CHECK-NO-ISEL-NEXT:    beq- 5, .LBB0_6
65; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %while.body392
66; CHECK-NO-ISEL-NEXT:    #
67; CHECK-NO-ISEL-NEXT:    bne- 1, .LBB0_5
68; CHECK-NO-ISEL-NEXT:  # %bb.3: # %wait_on_buffer.exit1319
69; CHECK-NO-ISEL-NEXT:    #
70; CHECK-NO-ISEL-NEXT:    ld 5, 0(6)
71; CHECK-NO-ISEL-NEXT:    mr 9, 5
72; CHECK-NO-ISEL-NEXT:    ldu 4, -72(9)
73; CHECK-NO-ISEL-NEXT:    andi. 4, 4, 1
74; CHECK-NO-ISEL-NEXT:    mr 4, 3
75; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB0_1
76; CHECK-NO-ISEL-NEXT:  # %bb.4: # %wait_on_buffer.exit1319
77; CHECK-NO-ISEL-NEXT:    #
78; CHECK-NO-ISEL-NEXT:    li 4, -5
79; CHECK-NO-ISEL-NEXT:    b .LBB0_1
80; CHECK-NO-ISEL-NEXT:  .LBB0_5:
81; CHECK-NO-ISEL-NEXT:    mr 4, 7
82; CHECK-NO-ISEL-NEXT:  .LBB0_6: # %while.end418
83; CHECK-NO-ISEL-NEXT:    cmplwi 4, 0
84; CHECK-NO-ISEL-NEXT:    beq 0, .LBB0_8
85; CHECK-NO-ISEL-NEXT:  # %bb.7: # %if.then420
86; CHECK-NO-ISEL-NEXT:  .LBB0_8: # %if.end421
87entry:
88  br label %while.body392
89
90while.body392:                                    ; preds = %wait_on_buffer.exit1319, %while.body392.lr.ph
91  %0 = load ptr, ptr %input4, align 8
92  %add.ptr399 = getelementptr inbounds i8, ptr %0, i64 -72
93  %ivar = add i32 %input1, 1
94  %tobool.i1316 = icmp eq i32 %input1, 0
95  br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %while.end418
96
97wait_on_buffer.exit1319:                          ; preds = %while.body392
98  %1 = load volatile i64, ptr %add.ptr399, align 8
99  %conv.i.i1322 = and i64 %1, 1
100  %lnot404 = icmp eq i64 %conv.i.i1322, 0
101  %.err.4 = select i1 %lnot404, i32 -5, i32 %input1
102  %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(ptr elementtype(i64) %add.ptr399, i64 262144, ptr %add.ptr399, ptr elementtype(i64) %add.ptr399) #0
103  store ptr %0, ptr %input4, align 8
104  %cmp.i1312 = icmp eq ptr %input2, %input3
105  br i1 %cmp.i1312, label %while.end418, label %while.body392
106
107while.end418:                                     ; preds = %wait_on_buffer.exit1319, %do.body378
108  %err.4.lcssa = phi i32 [ %ivar, %while.body392 ], [ %.err.4, %wait_on_buffer.exit1319 ]
109  %tobool419 = icmp eq i32 %err.4.lcssa, 0
110  br i1 %tobool419, label %if.end421, label %if.then420
111
112
113if.then420:                                       ; preds = %while.end418
114  unreachable
115
116if.end421:                                        ; preds = %while.end418
117  unreachable
118
119}
120
121attributes #0 = { nounwind }
122
123