1# RUN: llc -mcpu=pwr10 -enable-subreg-liveness -filetype=null \ 2# RUN: -mtriple=powerpc64le-unknown-linux-gnu -run-pass=greedy,virtregrewriter \ 3# RUN: -debug-only=regalloc -o - %s 2>&1 | FileCheck %s 4# REQUIRES: asserts 5 6# Keep track of all of the lanemasks for various subregsiters. 7# 8# CHECK: %3 [80r,80d:0) 0@80r L000000000000000C [80r,80d:0) 0@80r weight:0.000000e+00 9# CHECK: %4 [96r,96d:0) 0@96r L0000000000003000 [96r,96d:0) 0@96r weight:0.000000e+00 10# CHECK: %5 [112r,112d:0) 0@112r L000000000000000C [112r,112d:0) 0@112r weight:0.000000e+00 11# CHECK: %6 [128r,128d:0) 0@128r L0000000000003000 [128r,128d:0) 0@128r weight:0.000000e+00 12# CHECK: %7 [144r,144d:0) 0@144r L0000000000000004 [144r,144d:0) 0@144r weight:0.000000e+00 13# CHECK: %8 [160r,160d:0) 0@160r L0000000000001000 [160r,160d:0) 0@160r weight:0.000000e+00 14# CHECK: %9 [176r,176d:0) 0@176r L0000000000000004 [176r,176d:0) 0@176r weight:0.000000e+00 15# CHECK: %10 [192r,192d:0) 0@192r L0000000000001000 [192r,192d:0) 0@192r weight:0.000000e+00 16# CHECK: %11 [208r,208d:0) 0@208r L0000000000004000 [208r,208d:0) 0@208r weight:0.000000e+00 17# CHECK: %12 [224r,224d:0) 0@224r L0000000000010000 [224r,224d:0) 0@224r weight:0.000000e+00 18# CHECK: %13 [240r,240d:0) 0@240r L000000000000300C [240r,240d:0) 0@240r weight:0.000000e+00 19# CHECK: %14 [256r,256d:0) 0@256r L000000000003C000 [256r,256d:0) 0@256r weight:0.000000e+00 20 21 22# CHECK: 0B bb.0 23# CHECK-NEXT: liveins 24# CHECK-NEXT: 16B %0:vsrc = COPY $v2 25# CHECK-NEXT: 32B %float:fprc = COPY %0.sub_64:vsrc 26# CHECK-NEXT: 48B dead undef %pair.sub_vsx0:vsrprc = COPY $v2 27# CHECK-NEXT: 64B undef %15.sub_vsx1:vsrprc = COPY $v3 28# CHECK-NEXT: 80B dead undef %3.sub_vsx0:vsrprc = COPY %0:vsrc 29# CHECK-NEXT: 96B dead undef %4.sub_vsx1:vsrprc = COPY %0:vsrc 30# CHECK-NEXT: 112B dead undef %5.sub_vsx0:accrc = COPY %0:vsrc 31# CHECK-NEXT: 128B dead undef %6.sub_vsx1:accrc = COPY %0:vsrc 32# CHECK-NEXT: 144B dead undef %7.sub_64:vsrprc = COPY %float:fprc 33# CHECK-NEXT: 160B dead undef %8.sub_vsx1_then_sub_64:vsrprc = COPY %float:fprc 34# CHECK-NEXT: 176B dead undef %9.sub_64:accrc = COPY %float:fprc 35# CHECK-NEXT: 192B dead undef %10.sub_vsx1_then_sub_64:accrc = COPY %float:fprc 36# CHECK-NEXT: 208B dead undef %11.sub_pair1_then_sub_64:accrc = COPY %float:fprc 37# CHECK-NEXT: 224B dead undef %12.sub_pair1_then_sub_vsx1_then_sub_64:accrc = COPY %float:fprc 38# CHECK-NEXT: 240B dead undef %13.sub_pair0:accrc = COPY %15:vsrprc 39# CHECK-NEXT: 256B dead undef %14.sub_pair1:accrc = COPY %15:vsrprc 40 41 42--- 43name: test 44tracksRegLiveness: true 45body: | 46 bb.0: 47 liveins: $v2, $v3 48 %0:vsrc = COPY $v2 49 %float:fprc = COPY %0.sub_64 50 undef %pair.sub_vsx0:vsrprc = COPY $v2 51 undef %pair.sub_vsx1:vsrprc = COPY $v3 52 undef %1.sub_vsx0:vsrprc = COPY %0 53 undef %2.sub_vsx1:vsrprc = COPY %0 54 undef %3.sub_vsx0:accrc = COPY %0 55 undef %4.sub_vsx1:accrc = COPY %0 56 undef %5.sub_64:vsrprc = COPY %float 57 undef %6.sub_vsx1_then_sub_64:vsrprc = COPY %float 58 undef %7.sub_64:accrc = COPY %float 59 undef %8.sub_vsx1_then_sub_64:accrc = COPY %float 60 undef %9.sub_pair1_then_sub_64:accrc = COPY %float 61 undef %10.sub_pair1_then_sub_vsx1_then_sub_64:accrc = COPY %float 62 undef %11.sub_pair0:accrc = COPY %pair 63 undef %12.sub_pair1:accrc = COPY %pair 64... 65