1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 4; RUN: < %s | FileCheck %s --check-prefix=CHECK-LE 5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 7; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 8; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE 9 10define void @test1(<4 x i32> %A, ptr %a) { 11; CHECK-LE-LABEL: test1: 12; CHECK-LE: # %bb.0: # %entry 13; CHECK-LE-NEXT: stxvrwx v2, 0, r5 14; CHECK-LE-NEXT: blr 15; 16; CHECK-BE-LABEL: test1: 17; CHECK-BE: # %bb.0: # %entry 18; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 19; CHECK-BE-NEXT: stfiwx f0, 0, r5 20; CHECK-BE-NEXT: blr 21entry: 22 %vecext = extractelement <4 x i32> %A, i32 0 23 store i32 %vecext, ptr %a, align 4 24 ret void 25} 26 27define void @test2(<4 x float> %A, ptr %a) { 28; CHECK-LE-LABEL: test2: 29; CHECK-LE: # %bb.0: # %entry 30; CHECK-LE-NEXT: stxvrwx v2, 0, r5 31; CHECK-LE-NEXT: blr 32; 33; CHECK-BE-LABEL: test2: 34; CHECK-BE: # %bb.0: # %entry 35; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 36; CHECK-BE-NEXT: stfiwx f0, 0, r5 37; CHECK-BE-NEXT: blr 38entry: 39 %vecext = extractelement <4 x float> %A, i32 0 40 store float %vecext, ptr %a, align 4 41 ret void 42} 43 44define void @test3(<2 x double> %A, ptr %a) { 45; CHECK-LE-LABEL: test3: 46; CHECK-LE: # %bb.0: # %entry 47; CHECK-LE-NEXT: stxvrdx v2, 0, r5 48; CHECK-LE-NEXT: blr 49; 50; CHECK-BE-LABEL: test3: 51; CHECK-BE: # %bb.0: # %entry 52; CHECK-BE-NEXT: stxsd v2, 0(r5) 53; CHECK-BE-NEXT: blr 54entry: 55 %vecext = extractelement <2 x double> %A, i32 0 56 store double %vecext, ptr %a, align 8 57 ret void 58} 59 60define void @test4(<2 x i64> %A, ptr %a) { 61; CHECK-LE-LABEL: test4: 62; CHECK-LE: # %bb.0: # %entry 63; CHECK-LE-NEXT: stxvrdx v2, 0, r5 64; CHECK-LE-NEXT: blr 65; 66; CHECK-BE-LABEL: test4: 67; CHECK-BE: # %bb.0: # %entry 68; CHECK-BE-NEXT: stxsd v2, 0(r5) 69; CHECK-BE-NEXT: blr 70entry: 71 %vecext = extractelement <2 x i64> %A, i32 0 72 store i64 %vecext, ptr %a, align 8 73 ret void 74} 75 76define void @test5(<8 x i16> %A, ptr %a) { 77; CHECK-LE-LABEL: test5: 78; CHECK-LE: # %bb.0: # %entry 79; CHECK-LE-NEXT: stxvrhx v2, 0, r5 80; CHECK-LE-NEXT: blr 81; 82; CHECK-BE-LABEL: test5: 83; CHECK-BE: # %bb.0: # %entry 84; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 85; CHECK-BE-NEXT: stxsihx v2, 0, r5 86; CHECK-BE-NEXT: blr 87entry: 88 %vecext = extractelement <8 x i16> %A, i32 0 89 store i16 %vecext, ptr %a, align 2 90 ret void 91} 92 93define void @test6(<16 x i8> %A, ptr %a) { 94; CHECK-LE-LABEL: test6: 95; CHECK-LE: # %bb.0: # %entry 96; CHECK-LE-NEXT: stxvrbx v2, 0, r5 97; CHECK-LE-NEXT: blr 98; 99; CHECK-BE-LABEL: test6: 100; CHECK-BE: # %bb.0: # %entry 101; CHECK-BE-NEXT: vsldoi v2, v2, v2, 9 102; CHECK-BE-NEXT: stxsibx v2, 0, r5 103; CHECK-BE-NEXT: blr 104entry: 105 %vecext = extractelement <16 x i8> %A, i32 0 106 store i8 %vecext, ptr %a, align 1 107 ret void 108} 109 110