xref: /llvm-project/llvm/test/CodeGen/PowerPC/store-forward-be64.ll (revision a51712751c184ebe056718c938d2526693a31564) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=generic -verify-machineinstrs < %s | FileCheck %s
3
4target datalayout = "E-m:a-i64:64-n32:64-S128-v256:256:256-v512:512:512"
5target triple = "powerpc64-ibm-aix7.2.0.0"
6
7%struct.USST = type { i16, i16 }
8%struct.SST = type { i16, i16 }
9%struct.CST = type { i8, i8 }
10%struct.SCST = type { i8, i8 }
11%struct.ST = type { i32, i32 }
12%struct.UST = type { i32, i32 }
13%struct.LST = type { i64, i64 }
14%struct.ULST = type { i64, i64 }
15
16; Function Attrs: nounwind
17define zeroext i32 @ustc1(ptr noundef byval(%struct.USST) align 8 %s) {
18; CHECK-LABEL: ustc1:
19; CHECK:       # %bb.0: # %entry
20; CHECK-NEXT:    mr 4, 3
21; CHECK-NEXT:    rldicl 3, 3, 8, 56
22; CHECK-NEXT:    std 4, 48(1)
23; CHECK-NEXT:    blr
24entry:
25  %0 = load i16, ptr %s, align 8
26  %conv = zext i16 %0 to i32
27  %shr = ashr i32 %conv, 8
28  ret i32 %shr
29}
30
31; Function Attrs: nounwind
32define zeroext i32 @ustc2(ptr noundef byval(%struct.USST) align 8 %s) {
33; CHECK-LABEL: ustc2:
34; CHECK:       # %bb.0: # %entry
35; CHECK-NEXT:    mr 4, 3
36; CHECK-NEXT:    rldicl 3, 3, 16, 48
37; CHECK-NEXT:    std 4, 48(1)
38; CHECK-NEXT:    blr
39entry:
40  %0 = load i16, ptr %s, align 8
41  %conv = zext i16 %0 to i32
42  ret i32 %conv
43}
44
45; Function Attrs: nounwind
46define signext i32 @stc1(ptr noundef byval(%struct.SST) align 8 %s) {
47; CHECK-LABEL: stc1:
48; CHECK:       # %bb.0: # %entry
49; CHECK-NEXT:    mr 4, 3
50; CHECK-NEXT:    rldicl 3, 3, 16, 48
51; CHECK-NEXT:    std 4, 48(1)
52; CHECK-NEXT:    extsh 3, 3
53; CHECK-NEXT:    srawi 3, 3, 8
54; CHECK-NEXT:    blr
55entry:
56  %0 = load i16, ptr %s, align 8
57  %conv = sext i16 %0 to i32
58  %shr = ashr i32 %conv, 8
59  ret i32 %shr
60}
61
62; Function Attrs: nounwind
63define signext i32 @stc2(ptr noundef byval(%struct.SST) align 8 %s) {
64; CHECK-LABEL: stc2:
65; CHECK:       # %bb.0: # %entry
66; CHECK-NEXT:    mr 4, 3
67; CHECK-NEXT:    sradi 3, 3, 48
68; CHECK-NEXT:    std 4, 48(1)
69; CHECK-NEXT:    blr
70entry:
71  %0 = load i16, ptr %s, align 8
72  %conv = sext i16 %0 to i32
73  ret i32 %conv
74}
75
76; Function Attrs: nounwind
77define signext i32 @ctc(ptr noundef byval(%struct.CST) align 8 %s) {
78; CHECK-LABEL: ctc:
79; CHECK:       # %bb.0: # %entry
80; CHECK-NEXT:    mr 4, 3
81; CHECK-NEXT:    rldicl 3, 3, 8, 56
82; CHECK-NEXT:    std 4, 48(1)
83; CHECK-NEXT:    blr
84entry:
85  %0 = load i8, ptr %s, align 8
86  %conv = zext i8 %0 to i32
87  ret i32 %conv
88}
89
90; Function Attrs: nounwind
91define signext i32 @sctc(ptr noundef byval(%struct.SCST) align 8 %s) {
92; CHECK-LABEL: sctc:
93; CHECK:       # %bb.0: # %entry
94; CHECK-NEXT:    mr 4, 3
95; CHECK-NEXT:    sradi 3, 3, 56
96; CHECK-NEXT:    std 4, 48(1)
97; CHECK-NEXT:    blr
98entry:
99  %0 = load i8, ptr %s, align 8
100  %conv = sext i8 %0 to i32
101  ret i32 %conv
102}
103
104; Function Attrs: nounwind
105define signext i32 @tc44(ptr noundef byval(%struct.ST) align 8 %s) {
106; CHECK-LABEL: tc44:
107; CHECK:       # %bb.0: # %entry
108; CHECK-NEXT:    mr 4, 3
109; CHECK-NEXT:    sradi 3, 3, 32
110; CHECK-NEXT:    std 4, 48(1)
111; CHECK-NEXT:    blr
112entry:
113  %0 = load i32, ptr %s, align 8
114  ret i32 %0
115}
116
117; Function Attrs: nounwind
118define signext i32 @tc41(ptr noundef byval(%struct.ST) align 8 %s) {
119; CHECK-LABEL: tc41:
120; CHECK:       # %bb.0: # %entry
121; CHECK-NEXT:    mr 4, 3
122; CHECK-NEXT:    sradi 3, 3, 56
123; CHECK-NEXT:    std 4, 48(1)
124; CHECK-NEXT:    blr
125entry:
126  %0 = load i32, ptr %s, align 8
127  %shr = ashr i32 %0, 24
128  ret i32 %shr
129}
130
131; Function Attrs: nounwind
132define signext i32 @tc42(ptr noundef byval(%struct.ST) align 8 %s) {
133; CHECK-LABEL: tc42:
134; CHECK:       # %bb.0: # %entry
135; CHECK-NEXT:    mr 4, 3
136; CHECK-NEXT:    sradi 3, 3, 48
137; CHECK-NEXT:    std 4, 48(1)
138; CHECK-NEXT:    blr
139entry:
140  %0 = load i32, ptr %s, align 8
141  %shr = ashr i32 %0, 16
142  ret i32 %shr
143}
144
145; Function Attrs: nounwind
146define signext i32 @tc43(ptr noundef byval(%struct.ST) align 8 %s) {
147; CHECK-LABEL: tc43:
148; CHECK:       # %bb.0: # %entry
149; CHECK-NEXT:    mr 4, 3
150; CHECK-NEXT:    sradi 3, 3, 40
151; CHECK-NEXT:    std 4, 48(1)
152; CHECK-NEXT:    blr
153entry:
154  %0 = load i32, ptr %s, align 8
155  %shr = ashr i32 %0, 8
156  ret i32 %shr
157}
158
159; Function Attrs: nounwind
160define zeroext i32 @utc44(ptr noundef byval(%struct.UST) align 8 %s) #0 {
161; CHECK-LABEL: utc44:
162; CHECK:       # %bb.0: # %entry
163; CHECK-NEXT:    mr 4, 3
164; CHECK-NEXT:    rldicl 3, 3, 32, 32
165; CHECK-NEXT:    std 4, 48(1)
166; CHECK-NEXT:    blr
167entry:
168  %0 = load i32, ptr %s, align 8
169  ret i32 %0
170}
171
172; Function Attrs: nounwind
173define zeroext i32 @utc41(ptr noundef byval(%struct.UST) align 8 %s) {
174; CHECK-LABEL: utc41:
175; CHECK:       # %bb.0: # %entry
176; CHECK-NEXT:    mr 4, 3
177; CHECK-NEXT:    rldicl 3, 3, 8, 56
178; CHECK-NEXT:    std 4, 48(1)
179; CHECK-NEXT:    blr
180entry:
181  %0 = load i32, ptr %s, align 8
182  %shr = lshr i32 %0, 24
183  ret i32 %shr
184}
185
186; Function Attrs: nounwind
187define zeroext i32 @utc42(ptr noundef byval(%struct.UST) align 8 %s) {
188; CHECK-LABEL: utc42:
189; CHECK:       # %bb.0: # %entry
190; CHECK-NEXT:    mr 4, 3
191; CHECK-NEXT:    rldicl 3, 3, 16, 48
192; CHECK-NEXT:    std 4, 48(1)
193; CHECK-NEXT:    blr
194entry:
195  %0 = load i32, ptr %s, align 8
196  %shr = lshr i32 %0, 16
197  ret i32 %shr
198}
199
200; Function Attrs: nounwind
201define zeroext i32 @utc43(ptr noundef byval(%struct.UST) align 8 %s) {
202; CHECK-LABEL: utc43:
203; CHECK:       # %bb.0: # %entry
204; CHECK-NEXT:    mr 4, 3
205; CHECK-NEXT:    rldicl 3, 3, 24, 40
206; CHECK-NEXT:    std 4, 48(1)
207; CHECK-NEXT:    blr
208entry:
209  %0 = load i32, ptr %s, align 8
210  %shr = lshr i32 %0, 8
211  ret i32 %shr
212}
213
214; Function Attrs: nounwind
215define i64 @ltc88(ptr noundef byval(%struct.LST) align 8 %s) {
216; CHECK-LABEL: ltc88:
217; CHECK:       # %bb.0: # %entry
218; CHECK-NEXT:    mr 5, 3
219; CHECK-NEXT:    sradi 3, 3, 8
220; CHECK-NEXT:    std 5, 48(1)
221; CHECK-NEXT:    std 4, 56(1)
222; CHECK-NEXT:    blr
223entry:
224  %0 = load i64, ptr %s, align 8
225  %shr = ashr i64 %0, 8
226  ret i64 %shr
227}
228
229; Function Attrs: nounwind
230define i64 @ltc86(ptr noundef byval(%struct.LST) align 8 %s) {
231; CHECK-LABEL: ltc86:
232; CHECK:       # %bb.0: # %entry
233; CHECK-NEXT:    mr 5, 3
234; CHECK-NEXT:    sradi 3, 3, 16
235; CHECK-NEXT:    std 5, 48(1)
236; CHECK-NEXT:    std 4, 56(1)
237; CHECK-NEXT:    blr
238entry:
239  %0 = load i64, ptr %s, align 8
240  %shr = ashr i64 %0, 16
241  ret i64 %shr
242}
243
244; Function Attrs: nounwind
245define i64 @ltc85(ptr noundef byval(%struct.LST) align 8 %s) {
246; CHECK-LABEL: ltc85:
247; CHECK:       # %bb.0: # %entry
248; CHECK-NEXT:    mr 5, 3
249; CHECK-NEXT:    sradi 3, 3, 24
250; CHECK-NEXT:    std 5, 48(1)
251; CHECK-NEXT:    std 4, 56(1)
252; CHECK-NEXT:    blr
253entry:
254  %0 = load i64, ptr %s, align 8
255  %shr = ashr i64 %0, 24
256  ret i64 %shr
257}
258
259; Function Attrs: nounwind
260define i64 @ltc84(ptr noundef byval(%struct.LST) align 8 %s) {
261; CHECK-LABEL: ltc84:
262; CHECK:       # %bb.0: # %entry
263; CHECK-NEXT:    mr 5, 3
264; CHECK-NEXT:    sradi 3, 3, 32
265; CHECK-NEXT:    std 5, 48(1)
266; CHECK-NEXT:    std 4, 56(1)
267; CHECK-NEXT:    blr
268entry:
269  %0 = load i64, ptr %s, align 8
270  %shr = ashr i64 %0, 32
271  ret i64 %shr
272}
273
274; Function Attrs: nounwind
275define i64 @ltc83(ptr noundef byval(%struct.LST) align 8 %s) {
276; CHECK-LABEL: ltc83:
277; CHECK:       # %bb.0: # %entry
278; CHECK-NEXT:    mr 5, 3
279; CHECK-NEXT:    sradi 3, 3, 40
280; CHECK-NEXT:    std 5, 48(1)
281; CHECK-NEXT:    std 4, 56(1)
282; CHECK-NEXT:    blr
283entry:
284  %0 = load i64, ptr %s, align 8
285  %shr = ashr i64 %0, 40
286  ret i64 %shr
287}
288
289; Function Attrs: nounwind
290define i64 @ltc82(ptr noundef byval(%struct.LST) align 8 %s) {
291; CHECK-LABEL: ltc82:
292; CHECK:       # %bb.0: # %entry
293; CHECK-NEXT:    mr 5, 3
294; CHECK-NEXT:    sradi 3, 3, 48
295; CHECK-NEXT:    std 5, 48(1)
296; CHECK-NEXT:    std 4, 56(1)
297; CHECK-NEXT:    blr
298entry:
299  %0 = load i64, ptr %s, align 8
300  %shr = ashr i64 %0, 48
301  ret i64 %shr
302}
303
304; Function Attrs: nounwind
305define i64 @ltc81(ptr noundef byval(%struct.LST) align 8 %s) {
306; CHECK-LABEL: ltc81:
307; CHECK:       # %bb.0: # %entry
308; CHECK-NEXT:    mr 5, 3
309; CHECK-NEXT:    sradi 3, 3, 56
310; CHECK-NEXT:    std 5, 48(1)
311; CHECK-NEXT:    std 4, 56(1)
312; CHECK-NEXT:    blr
313entry:
314  %0 = load i64, ptr %s, align 8
315  %shr = ashr i64 %0, 56
316  ret i64 %shr
317}
318
319; Function Attrs: nounwind
320define i64 @ultc88(ptr noundef byval(%struct.ULST) align 8 %s) {
321; CHECK-LABEL: ultc88:
322; CHECK:       # %bb.0: # %entry
323; CHECK-NEXT:    std 3, 48(1)
324; CHECK-NEXT:    std 4, 56(1)
325; CHECK-NEXT:    blr
326entry:
327  %0 = load i64, ptr %s, align 8
328  ret i64 %0
329}
330
331; Function Attrs: nounwind
332define i64 @ultc87(ptr noundef byval(%struct.ULST) align 8 %s) {
333; CHECK-LABEL: ultc87:
334; CHECK:       # %bb.0: # %entry
335; CHECK-NEXT:    mr 5, 3
336; CHECK-NEXT:    rldicl 3, 3, 56, 8
337; CHECK-NEXT:    std 5, 48(1)
338; CHECK-NEXT:    std 4, 56(1)
339; CHECK-NEXT:    blr
340entry:
341  %0 = load i64, ptr %s, align 8
342  %shr = lshr i64 %0, 8
343  ret i64 %shr
344}
345
346; Function Attrs: nounwind
347define i64 @ultc86(ptr noundef byval(%struct.ULST) align 8 %s) {
348; CHECK-LABEL: ultc86:
349; CHECK:       # %bb.0: # %entry
350; CHECK-NEXT:    mr 5, 3
351; CHECK-NEXT:    rldicl 3, 3, 48, 16
352; CHECK-NEXT:    std 5, 48(1)
353; CHECK-NEXT:    std 4, 56(1)
354; CHECK-NEXT:    blr
355entry:
356  %0 = load i64, ptr %s, align 8
357  %shr = lshr i64 %0, 16
358  ret i64 %shr
359}
360
361; Function Attrs: nounwind
362define i64 @ultc85(ptr noundef byval(%struct.ULST) align 8 %s) {
363; CHECK-LABEL: ultc85:
364; CHECK:       # %bb.0: # %entry
365; CHECK-NEXT:    mr 5, 3
366; CHECK-NEXT:    rldicl 3, 3, 40, 24
367; CHECK-NEXT:    std 5, 48(1)
368; CHECK-NEXT:    std 4, 56(1)
369; CHECK-NEXT:    blr
370entry:
371  %0 = load i64, ptr %s, align 8
372  %shr = lshr i64 %0, 24
373  ret i64 %shr
374}
375
376; Function Attrs: nounwind
377define i64 @ultc84(ptr noundef byval(%struct.ULST) align 8 %s) {
378; CHECK-LABEL: ultc84:
379; CHECK:       # %bb.0: # %entry
380; CHECK-NEXT:    mr 5, 3
381; CHECK-NEXT:    rldicl 3, 3, 32, 32
382; CHECK-NEXT:    std 5, 48(1)
383; CHECK-NEXT:    std 4, 56(1)
384; CHECK-NEXT:    blr
385entry:
386  %0 = load i64, ptr %s, align 8
387  %shr = lshr i64 %0, 32
388  ret i64 %shr
389}
390
391; Function Attrs: nounwind
392define i64 @ultc83(ptr noundef byval(%struct.ULST) align 8 %s) {
393; CHECK-LABEL: ultc83:
394; CHECK:       # %bb.0: # %entry
395; CHECK-NEXT:    mr 5, 3
396; CHECK-NEXT:    rldicl 3, 3, 24, 40
397; CHECK-NEXT:    std 5, 48(1)
398; CHECK-NEXT:    std 4, 56(1)
399; CHECK-NEXT:    blr
400entry:
401  %0 = load i64, ptr %s, align 8
402  %shr = lshr i64 %0, 40
403  ret i64 %shr
404}
405
406; Function Attrs: nounwind
407define i64 @ultc82(ptr noundef byval(%struct.ULST) align 8 %s) {
408; CHECK-LABEL: ultc82:
409; CHECK:       # %bb.0: # %entry
410; CHECK-NEXT:    mr 5, 3
411; CHECK-NEXT:    rldicl 3, 3, 16, 48
412; CHECK-NEXT:    std 5, 48(1)
413; CHECK-NEXT:    std 4, 56(1)
414; CHECK-NEXT:    blr
415entry:
416  %0 = load i64, ptr %s, align 8
417  %shr = lshr i64 %0, 48
418  ret i64 %shr
419}
420
421; Function Attrs: nounwind
422define i64 @ultc81(ptr noundef byval(%struct.ULST) align 8 %s) {
423; CHECK-LABEL: ultc81:
424; CHECK:       # %bb.0: # %entry
425; CHECK-NEXT:    mr 5, 3
426; CHECK-NEXT:    rldicl 3, 3, 8, 56
427; CHECK-NEXT:    std 5, 48(1)
428; CHECK-NEXT:    std 4, 56(1)
429; CHECK-NEXT:    blr
430entry:
431  %0 = load i64, ptr %s, align 8
432  %shr = lshr i64 %0, 56
433  ret i64 %shr
434}
435