1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=generic -verify-machineinstrs < %s | FileCheck %s 3 4target datalayout = "E-m:a-p:32:32-i64:64-n32" 5target triple = "powerpc-ibm-aix7.2.0.0" 6 7%struct.USST = type { i16, i16 } 8%struct.SST = type { i16, i16 } 9%struct.CST = type { i8, i8 } 10%struct.SCST = type { i8, i8 } 11%struct.ST = type { i32, i32 } 12%struct.UST = type { i32, i32 } 13 14; Function Attrs: nounwind 15define i32 @ustc1(ptr noundef byval(%struct.USST) align 4 %s) { 16; CHECK-LABEL: ustc1: 17; CHECK: # %bb.0: # %entry 18; CHECK-NEXT: mr 4, 3 19; CHECK-NEXT: srwi 3, 3, 24 20; CHECK-NEXT: stw 4, 24(1) 21; CHECK-NEXT: blr 22entry: 23 %0 = load i16, ptr %s, align 4 24 %conv = zext i16 %0 to i32 25 %shr = ashr i32 %conv, 8 26 ret i32 %shr 27} 28 29; Function Attrs: nounwind 30define i32 @ustc2(ptr noundef byval(%struct.USST) align 4 %s) { 31; CHECK-LABEL: ustc2: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: mr 4, 3 34; CHECK-NEXT: srwi 3, 3, 16 35; CHECK-NEXT: stw 4, 24(1) 36; CHECK-NEXT: blr 37entry: 38 %0 = load i16, ptr %s, align 4 39 %conv = zext i16 %0 to i32 40 ret i32 %conv 41} 42 43; Function Attrs: nounwind 44define i32 @stc1(ptr noundef byval(%struct.SST) align 4 %s) { 45; CHECK-LABEL: stc1: 46; CHECK: # %bb.0: # %entry 47; CHECK-NEXT: mr 4, 3 48; CHECK-NEXT: srawi 3, 3, 24 49; CHECK-NEXT: stw 4, 24(1) 50; CHECK-NEXT: blr 51entry: 52 %0 = load i16, ptr %s, align 4 53 %conv = sext i16 %0 to i32 54 %shr = ashr i32 %conv, 8 55 ret i32 %shr 56} 57 58; Function Attrs: nounwind 59define i32 @stc2(ptr noundef byval(%struct.SST) align 4 %s) { 60; CHECK-LABEL: stc2: 61; CHECK: # %bb.0: # %entry 62; CHECK-NEXT: mr 4, 3 63; CHECK-NEXT: srawi 3, 3, 16 64; CHECK-NEXT: stw 4, 24(1) 65; CHECK-NEXT: blr 66entry: 67 %0 = load i16, ptr %s, align 4 68 %conv = sext i16 %0 to i32 69 ret i32 %conv 70} 71 72; Function Attrs: nounwind 73define i32 @ctc(ptr noundef byval(%struct.CST) align 4 %s) { 74; CHECK-LABEL: ctc: 75; CHECK: # %bb.0: # %entry 76; CHECK-NEXT: mr 4, 3 77; CHECK-NEXT: srwi 3, 3, 24 78; CHECK-NEXT: stw 4, 24(1) 79; CHECK-NEXT: blr 80entry: 81 %0 = load i8, ptr %s, align 4 82 %conv = zext i8 %0 to i32 83 ret i32 %conv 84} 85 86; Function Attrs: nounwind 87define i32 @sctc(ptr noundef byval(%struct.SCST) align 4 %s) { 88; CHECK-LABEL: sctc: 89; CHECK: # %bb.0: # %entry 90; CHECK-NEXT: mr 4, 3 91; CHECK-NEXT: srawi 3, 3, 24 92; CHECK-NEXT: stw 4, 24(1) 93; CHECK-NEXT: blr 94entry: 95 %0 = load i8, ptr %s, align 4 96 %conv = sext i8 %0 to i32 97 ret i32 %conv 98} 99 100; Function Attrs: nounwind 101define i32 @tc44(ptr noundef byval(%struct.ST) align 4 %s) { 102; CHECK-LABEL: tc44: 103; CHECK: # %bb.0: # %entry 104; CHECK-NEXT: stw 3, 24(1) 105; CHECK-NEXT: stw 4, 28(1) 106; CHECK-NEXT: blr 107entry: 108 %0 = load i32, ptr %s, align 4 109 ret i32 %0 110} 111 112; Function Attrs: nounwind 113define i32 @tc41(ptr noundef byval(%struct.ST) align 4 %s) { 114; CHECK-LABEL: tc41: 115; CHECK: # %bb.0: # %entry 116; CHECK-NEXT: stw 3, 24(1) 117; CHECK-NEXT: srawi 3, 3, 24 118; CHECK-NEXT: stw 4, 28(1) 119; CHECK-NEXT: blr 120entry: 121 %0 = load i32, ptr %s, align 4 122 %shr = ashr i32 %0, 24 123 ret i32 %shr 124} 125 126; Function Attrs: nounwind 127define i32 @tc42(ptr noundef byval(%struct.ST) align 4 %s) { 128; CHECK-LABEL: tc42: 129; CHECK: # %bb.0: # %entry 130; CHECK-NEXT: stw 3, 24(1) 131; CHECK-NEXT: srawi 3, 3, 16 132; CHECK-NEXT: stw 4, 28(1) 133; CHECK-NEXT: blr 134entry: 135 %0 = load i32, ptr %s, align 4 136 %shr = ashr i32 %0, 16 137 ret i32 %shr 138} 139 140; Function Attrs: nounwind 141define i32 @tc43(ptr noundef byval(%struct.ST) align 4 %s) { 142; CHECK-LABEL: tc43: 143; CHECK: # %bb.0: # %entry 144; CHECK-NEXT: stw 3, 24(1) 145; CHECK-NEXT: srawi 3, 3, 8 146; CHECK-NEXT: stw 4, 28(1) 147; CHECK-NEXT: blr 148entry: 149 %0 = load i32, ptr %s, align 4 150 %shr = ashr i32 %0, 8 151 ret i32 %shr 152} 153 154; Function Attrs: nounwind 155define i32 @utc44(ptr noundef byval(%struct.UST) align 4 %s) { 156; CHECK-LABEL: utc44: 157; CHECK: # %bb.0: # %entry 158; CHECK-NEXT: stw 3, 24(1) 159; CHECK-NEXT: stw 4, 28(1) 160; CHECK-NEXT: blr 161entry: 162 %0 = load i32, ptr %s, align 4 163 ret i32 %0 164} 165 166; Function Attrs: nounwind 167define i32 @utc41(ptr noundef byval(%struct.UST) align 4 %s) { 168; CHECK-LABEL: utc41: 169; CHECK: # %bb.0: # %entry 170; CHECK-NEXT: stw 3, 24(1) 171; CHECK-NEXT: srwi 3, 3, 24 172; CHECK-NEXT: stw 4, 28(1) 173; CHECK-NEXT: blr 174entry: 175 %0 = load i32, ptr %s, align 4 176 %shr = lshr i32 %0, 24 177 ret i32 %shr 178} 179 180; Function Attrs: nounwind 181define i32 @utc42(ptr noundef byval(%struct.UST) align 4 %s) { 182; CHECK-LABEL: utc42: 183; CHECK: # %bb.0: # %entry 184; CHECK-NEXT: stw 3, 24(1) 185; CHECK-NEXT: srwi 3, 3, 16 186; CHECK-NEXT: stw 4, 28(1) 187; CHECK-NEXT: blr 188entry: 189 %0 = load i32, ptr %s, align 4 190 %shr = lshr i32 %0, 16 191 ret i32 %shr 192} 193 194; Function Attrs: nounwind 195define i32 @utc43(ptr noundef byval(%struct.UST) align 4 %s) { 196; CHECK-LABEL: utc43: 197; CHECK: # %bb.0: # %entry 198; CHECK-NEXT: stw 3, 24(1) 199; CHECK-NEXT: srwi 3, 3, 8 200; CHECK-NEXT: stw 4, 28(1) 201; CHECK-NEXT: blr 202entry: 203 %0 = load i32, ptr %s, align 4 204 %shr = lshr i32 %0, 8 205 ret i32 %shr 206} 207