xref: /llvm-project/llvm/test/CodeGen/PowerPC/srem-lkk.ll (revision eb7d16ea25649909373e324e6ebf36774cabdbfa)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck --check-prefix=CHECK %s
3; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck --check-prefix=CHECK %s
4
5define i32 @fold_srem_positive_odd(i32 %x) {
6; CHECK-LABEL: fold_srem_positive_odd:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    lis 4, -21386
9; CHECK-NEXT:    ori 4, 4, 37253
10; CHECK-NEXT:    mulhw 4, 3, 4
11; CHECK-NEXT:    add 4, 4, 3
12; CHECK-NEXT:    srwi 5, 4, 31
13; CHECK-NEXT:    srawi 4, 4, 6
14; CHECK-NEXT:    add 4, 4, 5
15; CHECK-NEXT:    mulli 4, 4, 95
16; CHECK-NEXT:    sub 3, 3, 4
17; CHECK-NEXT:    blr
18  %1 = srem i32 %x, 95
19  ret i32 %1
20}
21
22
23define i32 @fold_srem_positive_even(i32 %x) {
24; CHECK-LABEL: fold_srem_positive_even:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    lis 4, 15827
27; CHECK-NEXT:    ori 4, 4, 36849
28; CHECK-NEXT:    mulhw 4, 3, 4
29; CHECK-NEXT:    srwi 5, 4, 31
30; CHECK-NEXT:    srawi 4, 4, 8
31; CHECK-NEXT:    add 4, 4, 5
32; CHECK-NEXT:    mulli 4, 4, 1060
33; CHECK-NEXT:    sub 3, 3, 4
34; CHECK-NEXT:    blr
35  %1 = srem i32 %x, 1060
36  ret i32 %1
37}
38
39
40define i32 @fold_srem_negative_odd(i32 %x) {
41; CHECK-LABEL: fold_srem_negative_odd:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    lis 4, -23206
44; CHECK-NEXT:    ori 4, 4, 65445
45; CHECK-NEXT:    mulhw 4, 3, 4
46; CHECK-NEXT:    srwi 5, 4, 31
47; CHECK-NEXT:    srawi 4, 4, 8
48; CHECK-NEXT:    add 4, 4, 5
49; CHECK-NEXT:    mulli 4, 4, -723
50; CHECK-NEXT:    sub 3, 3, 4
51; CHECK-NEXT:    blr
52  %1 = srem i32 %x, -723
53  ret i32 %1
54}
55
56
57define i32 @fold_srem_negative_even(i32 %x) {
58; CHECK-LABEL: fold_srem_negative_even:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    lis 4, -731
61; CHECK-NEXT:    ori 4, 4, 62439
62; CHECK-NEXT:    mulhw 4, 3, 4
63; CHECK-NEXT:    srwi 5, 4, 31
64; CHECK-NEXT:    srawi 4, 4, 8
65; CHECK-NEXT:    add 4, 4, 5
66; CHECK-NEXT:    mulli 4, 4, -22981
67; CHECK-NEXT:    sub 3, 3, 4
68; CHECK-NEXT:    blr
69  %1 = srem i32 %x, -22981
70  ret i32 %1
71}
72
73
74; Don't fold if we can combine srem with sdiv.
75define i32 @combine_srem_sdiv(i32 %x) {
76; CHECK-LABEL: combine_srem_sdiv:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    lis 4, -21386
79; CHECK-NEXT:    ori 4, 4, 37253
80; CHECK-NEXT:    mulhw 4, 3, 4
81; CHECK-NEXT:    add 4, 4, 3
82; CHECK-NEXT:    srwi 5, 4, 31
83; CHECK-NEXT:    srawi 4, 4, 6
84; CHECK-NEXT:    add 4, 4, 5
85; CHECK-NEXT:    mulli 5, 4, 95
86; CHECK-NEXT:    sub 3, 3, 5
87; CHECK-NEXT:    add 3, 3, 4
88; CHECK-NEXT:    blr
89  %1 = srem i32 %x, 95
90  %2 = sdiv i32 %x, 95
91  %3 = add i32 %1, %2
92  ret i32 %3
93}
94
95; Don't fold for divisors that are a power of two.
96define i32 @dont_fold_srem_power_of_two(i32 %x) {
97; CHECK-LABEL: dont_fold_srem_power_of_two:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    srawi 4, 3, 6
100; CHECK-NEXT:    addze 4, 4
101; CHECK-NEXT:    slwi 4, 4, 6
102; CHECK-NEXT:    sub 3, 3, 4
103; CHECK-NEXT:    blr
104  %1 = srem i32 %x, 64
105  ret i32 %1
106}
107
108; Don't fold if the divisor is one.
109define i32 @dont_fold_srem_one(i32 %x) {
110; CHECK-LABEL: dont_fold_srem_one:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    li 3, 0
113; CHECK-NEXT:    blr
114  %1 = srem i32 %x, 1
115  ret i32 %1
116}
117
118; Don't fold if the divisor is 2^31.
119define i32 @dont_fold_srem_i32_smax(i32 %x) {
120; CHECK-LABEL: dont_fold_srem_i32_smax:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    srawi 4, 3, 31
123; CHECK-NEXT:    addze 4, 4
124; CHECK-NEXT:    slwi 4, 4, 31
125; CHECK-NEXT:    add 3, 3, 4
126; CHECK-NEXT:    blr
127  %1 = srem i32 %x, 2147483648
128  ret i32 %1
129}
130
131; Don't fold i64 srem
132define i64 @dont_fold_srem_i64(i64 %x) {
133; CHECK-LABEL: dont_fold_srem_i64:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    mflr 0
136; CHECK-NEXT:    stwu 1, -16(1)
137; CHECK-NEXT:    stw 0, 20(1)
138; CHECK-NEXT:    .cfi_def_cfa_offset 16
139; CHECK-NEXT:    .cfi_offset lr, 4
140; CHECK-NEXT:    li 5, 0
141; CHECK-NEXT:    li 6, 98
142; CHECK-NEXT:    bl __moddi3
143; CHECK-NEXT:    lwz 0, 20(1)
144; CHECK-NEXT:    addi 1, 1, 16
145; CHECK-NEXT:    mtlr 0
146; CHECK-NEXT:    blr
147  %1 = srem i64 %x, 98
148  ret i64 %1
149}
150