xref: /llvm-project/llvm/test/CodeGen/PowerPC/split-index-tc.ll (revision 5403c59c608c08c8ecd4303763f08eb046eb5e4d)
1; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5%"class.llvm::MachineOperand" = type { i8, [3 x i8], i64, ptr, i64 }
6
7; Function Attrs: nounwind
8define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj() #0 align 2 {
9
10; If we were able to split out the indexing, the load with update should be
11; removed (resulting in a nearly-empty output).
12; CHECK-LABEL: @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj
13; CHECK-NOT: lhzu
14
15entry:
16  %0 = load ptr, ptr undef, align 8
17  br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123
18
19cond.false.i123:                                  ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
20  unreachable
21
22_ZNK4llvm14MachineOperand6getRegEv.exit:          ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
23  %IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", ptr %0, i64 undef, i32 1
24  %bf.load.i = load i24, ptr %IsDef.i, align 1
25  %1 = and i24 %bf.load.i, 128
26  br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph
27
28for.body.lr.ph:                                   ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
29  %2 = zext i24 %1 to i32
30  br i1 undef, label %cond.false.i134, label %_ZNK4llvm18MCRegAliasIteratordeEv.exit
31
32for.cond.cleanup:                                 ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit
33  br i1 undef, label %_ZNK4llvm14MachineOperand5isDefEv.exit, label %cond.false.i129
34
35cond.false.i129:                                  ; preds = %for.cond.cleanup
36  unreachable
37
38_ZNK4llvm14MachineOperand5isDefEv.exit:           ; preds = %for.cond.cleanup
39  br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit247, label %cond.false.i244
40
41cond.false.i134:                                  ; preds = %for.body.lr.ph
42  unreachable
43
44_ZNK4llvm18MCRegAliasIteratordeEv.exit:           ; preds = %for.body.lr.ph
45  unreachable
46
47cond.false.i244:                                  ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
48  unreachable
49
50_ZNK4llvm14MachineOperand6getRegEv.exit247:       ; preds = %_ZNK4llvm14MachineOperand5isDefEv.exit
51  br i1 undef, label %if.then53, label %if.end55
52
53if.then53:                                        ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
54  unreachable
55
56if.end55:                                         ; preds = %_ZNK4llvm14MachineOperand6getRegEv.exit247
57  br i1 undef, label %_ZNK4llvm14MachineOperand6isDeadEv.exit262, label %cond.false.i257
58
59cond.false.i257:                                  ; preds = %if.end55
60  unreachable
61
62_ZNK4llvm14MachineOperand6isDeadEv.exit262:       ; preds = %if.end55
63  %bf.load.i259 = load i24, ptr %IsDef.i, align 1
64  br i1 undef, label %if.then57, label %if.else59
65
66if.then57:                                        ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
67  unreachable
68
69if.else59:                                        ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262
70  br i1 undef, label %if.end89, label %if.then62
71
72if.then62:                                        ; preds = %if.else59
73  unreachable
74
75if.end89:                                         ; preds = %if.else59
76  unreachable
77}
78
79attributes #0 = { nounwind }
80
81
82