xref: /llvm-project/llvm/test/CodeGen/PowerPC/smulfixsat.ll (revision d1924f0474b65fe3189ffd658a12f452e4696c28)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ppc32 | FileCheck %s
3
4declare  i32 @llvm.smul.fix.sat.i32  (i32, i32, i32)
5
6define i32 @func1(i32 %x, i32 %y) nounwind {
7; CHECK-LABEL: func1:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    mulhw 5, 3, 4
10; CHECK-NEXT:    mullw 3, 3, 4
11; CHECK-NEXT:    srawi 4, 3, 31
12; CHECK-NEXT:    cmplw 5, 4
13; CHECK-NEXT:    beqlr 0
14; CHECK-NEXT:  # %bb.1:
15; CHECK-NEXT:    srawi 3, 5, 31
16; CHECK-NEXT:    xori 3, 3, 65535
17; CHECK-NEXT:    xoris 3, 3, 32767
18; CHECK-NEXT:    blr
19  %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0)
20  ret i32 %tmp
21}
22
23define i32 @func2(i32 %x, i32 %y) nounwind {
24; CHECK-LABEL: func2:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    mulhw. 5, 3, 4
27; CHECK-NEXT:    bgt 0, .LBB1_2
28; CHECK-NEXT:  # %bb.1:
29; CHECK-NEXT:    mullw 3, 3, 4
30; CHECK-NEXT:    rotlwi 4, 3, 31
31; CHECK-NEXT:    rlwimi 4, 5, 31, 0, 0
32; CHECK-NEXT:    b .LBB1_3
33; CHECK-NEXT:  .LBB1_2:
34; CHECK-NEXT:    lis 3, 32767
35; CHECK-NEXT:    ori 4, 3, 65535
36; CHECK-NEXT:  .LBB1_3:
37; CHECK-NEXT:    cmpwi 5, -1
38; CHECK-NEXT:    lis 3, -32768
39; CHECK-NEXT:    bltlr 0
40; CHECK-NEXT:  # %bb.4:
41; CHECK-NEXT:    mr 3, 4
42; CHECK-NEXT:    blr
43  %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 1)
44  ret i32 %tmp
45}
46