1# RUN: llc --verify-machineinstrs -mcpu=pwr9 -o - %s -run-pass=pipeliner -ppc-enable-pipeliner -pipeliner-register-pressure -pipeliner-max-mii=50 -pipeliner-ii-search-range=30 -pipeliner-max-stages=10 -debug-only=pipeliner 2>&1 | FileCheck %s 2 3# REQUIRES: asserts 4 5# Check that if the register pressure is too high, the schedule is rejected, II is incremented, and scheduling continues. 6# The specific value of II is not important. 7 8# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}} 9# CHECK: {{^ *}}Rejected the schedule because of too high register pressure{{$}} 10# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}} 11# CHECK: {{^ *}}Schedule Found? 1 (II={{[0-9]+}}){{$}} 12 13--- | 14 target datalayout = "e-m:e-Fn32-i64:64-n32:64" 15 target triple = "ppc64le" 16 17 define dso_local double @kernel(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef signext %n) local_unnamed_addr { 18 entry: 19 %0 = load double, ptr %a, align 8 20 %arrayidx1 = getelementptr inbounds i8, ptr %a, i64 8 21 %1 = load double, ptr %arrayidx1, align 8 22 %cmp163 = icmp sgt i32 %n, 0 23 br i1 %cmp163, label %for.body.preheader, label %for.cond.cleanup 24 25 for.body.preheader: ; preds = %entry 26 %wide.trip.count = zext nneg i32 %n to i64 27 %scevgep167 = getelementptr i8, ptr %b, i64 -8 28 call void @llvm.set.loop.iterations.i64(i64 %wide.trip.count) 29 br label %for.body 30 31 for.cond.cleanup: ; preds = %for.body, %entry 32 %res.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %30, %for.body ] 33 ret double %res.0.lcssa 34 35 for.body: ; preds = %for.body.preheader, %for.body 36 %res.0165 = phi double [ 0.000000e+00, %for.body.preheader ], [ %30, %for.body ] 37 %2 = phi ptr [ %scevgep167, %for.body.preheader ], [ %3, %for.body ] 38 %3 = getelementptr i8, ptr %2, i64 8 39 %4 = load double, ptr %3, align 8 40 %5 = tail call double @llvm.fmuladd.f64(double %0, double %4, double %0) 41 %6 = tail call double @llvm.fmuladd.f64(double %5, double %4, double %5) 42 %7 = tail call double @llvm.fmuladd.f64(double %6, double %4, double %6) 43 %8 = tail call double @llvm.fmuladd.f64(double %7, double %4, double %7) 44 %9 = tail call double @llvm.fmuladd.f64(double %8, double %4, double %8) 45 %10 = tail call double @llvm.fmuladd.f64(double %9, double %4, double %9) 46 %11 = tail call double @llvm.fmuladd.f64(double %10, double %4, double %10) 47 %12 = tail call double @llvm.fmuladd.f64(double %11, double %4, double %11) 48 %13 = tail call double @llvm.fmuladd.f64(double %12, double %4, double %12) 49 %14 = tail call double @llvm.fmuladd.f64(double %13, double %4, double %13) 50 %15 = tail call double @llvm.fmuladd.f64(double %14, double %4, double %14) 51 %16 = tail call double @llvm.fmuladd.f64(double %15, double %4, double %15) 52 %17 = tail call double @llvm.fmuladd.f64(double %16, double %4, double %16) 53 %18 = tail call double @llvm.fmuladd.f64(double %17, double %4, double %17) 54 %19 = tail call double @llvm.fmuladd.f64(double %18, double %4, double %18) 55 %20 = tail call double @llvm.fmuladd.f64(double %19, double %4, double %19) 56 %add = fadd double %19, %20 57 %21 = tail call double @llvm.fmuladd.f64(double %20, double %4, double %add) 58 %add35 = fadd double %12, %21 59 %22 = tail call double @llvm.fmuladd.f64(double %5, double %4, double %add35) 60 %add38 = fadd double %13, %22 61 %23 = tail call double @llvm.fmuladd.f64(double %6, double %4, double %add38) 62 %mul = fmul double %4, %7 63 %mul46 = fmul double %mul, %14 64 %24 = tail call double @llvm.fmuladd.f64(double %mul46, double %13, double %16) 65 %mul50 = fmul double %4, %9 66 %mul51 = fmul double %1, %mul50 67 %25 = tail call double @llvm.fmuladd.f64(double %mul51, double %11, double %24) 68 %add53 = fadd double %5, %25 69 %add54 = fadd double %6, %add53 70 %mul55 = fmul double %14, %16 71 %mul56 = fmul double %mul55, %17 72 %mul57 = fmul double %mul56, %18 73 %26 = tail call double @llvm.fmuladd.f64(double %mul57, double %19, double %add54) 74 %27 = tail call double @llvm.fmuladd.f64(double %10, double %1, double %26) 75 %28 = tail call double @llvm.fmuladd.f64(double %8, double %6, double %27) 76 %mul61 = fmul double %20, %21 77 %mul62 = fmul double %mul61, %22 78 %29 = tail call double @llvm.fmuladd.f64(double %mul62, double %23, double %28) 79 %mul64 = fmul double %26, %29 80 %mul65 = fmul double %24, %mul64 81 %mul66 = fmul double %12, %mul65 82 %30 = tail call double @llvm.fmuladd.f64(double %mul66, double %10, double %res.0165) 83 %31 = call i1 @llvm.loop.decrement.i64(i64 1) 84 br i1 %31, label %for.body, label %for.cond.cleanup 85 } 86 87 declare double @llvm.fmuladd.f64(double, double, double) 88 89 declare void @llvm.set.loop.iterations.i64(i64) 90 91 declare i1 @llvm.loop.decrement.i64(i64) 92 93... 94--- 95name: kernel 96tracksRegLiveness: true 97liveins: 98 - { reg: '$x3', virtual-reg: '%8' } 99 - { reg: '$x4', virtual-reg: '%9' } 100 - { reg: '$x5', virtual-reg: '%10' } 101body: | 102 bb.0.entry: 103 successors: %bb.2(0x50000000), %bb.1(0x30000000) 104 liveins: $x3, $x4, $x5 105 106 %10:g8rc = COPY killed $x5 107 %9:g8rc_and_g8rc_nox0 = COPY killed $x4 108 %8:g8rc_and_g8rc_nox0 = COPY killed $x3 109 %11:gprc = COPY killed %10.sub_32 110 %13:crrc = CMPWI %11, 0 111 BCC 44, killed %13, %bb.2 112 113 bb.1: 114 %12:vsfrc = XXLXORdpz 115 B %bb.3 116 117 bb.2.for.body.preheader: 118 %0:vsfrc = DFLOADf64 0, %8 :: (load (s64) from %ir.a) 119 %1:vsfrc = DFLOADf64 8, killed %8 :: (load (s64) from %ir.arrayidx1) 120 %16:g8rc = IMPLICIT_DEF 121 %15:g8rc = INSERT_SUBREG killed %16, killed %11, %subreg.sub_32 122 %17:g8rc = RLDICL killed %15, 0, 32 123 %2:g8rc = ADDI8 killed %9, -8 124 MTCTR8loop killed %17, implicit-def dead $ctr8 125 %14:vsfrc = XXLXORdpz 126 B %bb.4 127 128 bb.3.for.cond.cleanup: 129 %3:vsfrc = PHI %12, %bb.1, %7, %bb.4 130 $f1 = COPY killed %3 131 BLR8 implicit $lr8, implicit $rm, implicit killed $f1 132 133 bb.4.for.body: 134 successors: %bb.4(0x7c000000), %bb.3(0x04000000) 135 136 %4:vsfrc = PHI %14, %bb.2, %7, %bb.4 137 %5:g8rc_and_g8rc_nox0 = PHI %2, %bb.2, %6, %bb.4 138 %18:f8rc, %19:g8rc_and_g8rc_nox0 = LFDU 8, killed %5 :: (load (s64) from %ir.3) 139 %6:g8rc = COPY killed %19 140 %20:vsfrc = nofpexcept XSMADDADP %0, %0, %18, implicit $rm 141 %21:vsfrc = nofpexcept XSMADDADP %20, %20, %18, implicit $rm 142 %22:vsfrc = nofpexcept XSMADDADP %21, %21, %18, implicit $rm 143 %23:vsfrc = nofpexcept XSMADDADP %22, %22, %18, implicit $rm 144 %24:vsfrc = nofpexcept XSMADDADP %23, %23, %18, implicit $rm 145 %25:vsfrc = nofpexcept XSMADDADP %24, %24, %18, implicit $rm 146 %26:vsfrc = nofpexcept XSMADDADP %25, %25, %18, implicit $rm 147 %27:vsfrc = nofpexcept XSMADDADP %26, %26, %18, implicit $rm 148 %28:vsfrc = nofpexcept XSMADDADP %27, %27, %18, implicit $rm 149 %29:vsfrc = nofpexcept XSMADDADP %28, %28, %18, implicit $rm 150 %30:vsfrc = nofpexcept XSMADDADP %29, %29, %18, implicit $rm 151 %31:vsfrc = nofpexcept XSMADDADP killed %30, %30, %18, implicit $rm 152 %32:vsfrc = nofpexcept XSMADDADP %31, %31, %18, implicit $rm 153 %33:vsfrc = nofpexcept XSMADDADP %32, %32, %18, implicit $rm 154 %34:vsfrc = nofpexcept XSMADDADP %33, %33, %18, implicit $rm 155 %35:vsfrc = nofpexcept XSMADDADP %34, %34, %18, implicit $rm 156 %36:vsfrc = nofpexcept XSADDDP %34, %35, implicit $rm 157 %37:vsfrc = nofpexcept XSMADDADP killed %36, %35, %18, implicit $rm 158 %38:vsfrc = nofpexcept XSADDDP %27, %37, implicit $rm 159 %39:vsfrc = nofpexcept XSMADDADP killed %38, %20, %18, implicit $rm 160 %40:vsfrc = nofpexcept XSADDDP %28, %39, implicit $rm 161 %41:vsfrc = nofpexcept XSMADDADP killed %40, %21, %18, implicit $rm 162 %42:vsfrc = nofpexcept XSMULDP %18, killed %22, implicit $rm 163 %43:vsfrc = nofpexcept XSMULDP killed %42, %29, implicit $rm 164 %44:vsfrc = nofpexcept XSMADDADP %31, killed %43, killed %28, implicit $rm 165 %45:vsfrc = nofpexcept XSMULDP killed %18, killed %24, implicit $rm 166 %46:vsfrc = nofpexcept XSMULDP %1, killed %45, implicit $rm 167 %47:vsfrc = nofpexcept XSMADDADP %44, killed %46, killed %26, implicit $rm 168 %48:vsfrc = nofpexcept XSADDDP killed %20, killed %47, implicit $rm 169 %49:vsfrc = nofpexcept XSADDDP %21, killed %48, implicit $rm 170 %50:vsfrc = nofpexcept XSMULDP killed %29, killed %31, implicit $rm 171 %51:vsfrc = nofpexcept XSMULDP killed %50, killed %32, implicit $rm 172 %52:vsfrc = nofpexcept XSMULDP killed %51, killed %33, implicit $rm 173 %53:vsfrc = nofpexcept XSMADDADP killed %49, killed %52, killed %34, implicit $rm 174 %54:vsfrc = nofpexcept XSMADDADP %53, %25, %1, implicit $rm 175 %55:vsfrc = nofpexcept XSMADDADP killed %54, killed %23, killed %21, implicit $rm 176 %56:vsfrc = nofpexcept XSMULDP killed %35, killed %37, implicit $rm 177 %57:vsfrc = nofpexcept XSMULDP killed %56, killed %39, implicit $rm 178 %58:vsfrc = nofpexcept XSMADDADP killed %55, killed %57, killed %41, implicit $rm 179 %59:vsfrc = nofpexcept XSMULDP killed %53, killed %58, implicit $rm 180 %60:vsfrc = nofpexcept XSMULDP killed %44, killed %59, implicit $rm 181 %61:vsfrc = nofpexcept XSMULDP killed %27, killed %60, implicit $rm 182 %7:vsfrc = nofpexcept XSMADDADP killed %4, killed %61, killed %25, implicit $rm 183 BDNZ8 %bb.4, implicit-def $ctr8, implicit $ctr8 184 B %bb.3 185 186... 187