1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 --ppc-enable-pipeliner -pipeliner-max-stages=10 -run-pass=pipeliner -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK 3 4--- | 5 define dso_local void @f(ptr noalias nocapture noundef writeonly %a, ptr nocapture noundef readonly %b, i32 noundef signext %n) local_unnamed_addr #0 { 6 entry: 7 %wide.trip.count = zext i32 %n to i64 8 %uglygep2 = getelementptr i8, ptr %b, i64 -4 9 %uglygep3 = getelementptr i8, ptr %a, i64 -4 10 call void @llvm.set.loop.iterations.i64(i64 %wide.trip.count) 11 br label %for.body 12 13 for.cond.cleanup: ; preds = %for.body 14 ret void 15 16 for.body: ; preds = %for.body, %entry 17 %0 = phi ptr [ %uglygep2, %entry ], [ %3, %for.body ] 18 %1 = phi ptr [ %uglygep3, %entry ], [ %2, %for.body ] 19 %2 = getelementptr i8, ptr %1, i64 4 20 %3 = getelementptr i8, ptr %0, i64 4 21 %4 = load float, ptr %3, align 4 22 %add = fadd float %4, %4 23 %add3 = fadd float %4, %add 24 store float %add3, ptr %2, align 4 25 %5 = call i1 @llvm.loop.decrement.i64(i64 1) 26 br i1 %5, label %for.body, label %for.cond.cleanup, !llvm.loop !0 27 } 28 29 ; Function Attrs: nocallback noduplicate nofree nosync nounwind willreturn 30 declare void @llvm.set.loop.iterations.i64(i64) #1 31 32 ; Function Attrs: nocallback noduplicate nofree nosync nounwind willreturn 33 declare i1 @llvm.loop.decrement.i64(i64) #1 34 35 attributes #0 = { argmemonly nofree norecurse nosync nounwind uwtable "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+htm,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+power8-vector,+power9-vector,+quadword-atomics,+vsx,-privileged,-rop-protect,-spe" } 36 attributes #1 = { nocallback noduplicate nofree nosync nounwind willreturn } 37 38 !0 = distinct !{!0, !1, !2, !3} 39 !1 = !{!"llvm.loop.mustprogress"} 40 !2 = !{!"llvm.loop.unroll.disable"} 41 !3 = !{!"llvm.loop.pipeline.initiationinterval", i32 3} 42 43... 44--- 45name: f 46alignment: 16 47tracksRegLiveness: true 48registers: 49 - { id: 0, class: g8rc } 50 - { id: 1, class: g8rc } 51 - { id: 2, class: g8rc_and_g8rc_nox0 } 52 - { id: 3, class: g8rc_and_g8rc_nox0 } 53 - { id: 4, class: g8rc } 54 - { id: 5, class: g8rc } 55 - { id: 6, class: g8rc_and_g8rc_nox0 } 56 - { id: 7, class: g8rc_and_g8rc_nox0 } 57 - { id: 8, class: g8rc } 58 - { id: 9, class: g8rc } 59 - { id: 10, class: f4rc } 60 - { id: 11, class: g8rc_and_g8rc_nox0 } 61 - { id: 12, class: vssrc } 62 - { id: 13, class: f4rc } 63 - { id: 14, class: g8rc_and_g8rc_nox0 } 64liveins: 65 - { reg: '$x3', virtual-reg: '%6' } 66 - { reg: '$x4', virtual-reg: '%7' } 67 - { reg: '$x5', virtual-reg: '%8' } 68frameInfo: 69 maxAlignment: 1 70machineFunctionInfo: {} 71body: | 72 ; CHECK-LABEL: name: f 73 ; CHECK: bb.0.entry: 74 ; CHECK-NEXT: successors: %bb.3(0x80000000) 75 ; CHECK-NEXT: liveins: $x3, $x4, $x5 76 ; CHECK-NEXT: {{ $}} 77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x5 78 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x4 79 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3 80 ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 32 81 ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY1]], -4 82 ; CHECK-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 [[COPY2]], -4 83 ; CHECK-NEXT: MTCTR8loop [[RLDICL]], implicit-def dead $ctr8 84 ; CHECK-NEXT: B %bb.3 85 ; CHECK-NEXT: {{ $}} 86 ; CHECK-NEXT: bb.1.for.cond.cleanup: 87 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm 88 ; CHECK-NEXT: {{ $}} 89 ; CHECK-NEXT: bb.3.for.body: 90 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.17(0x40000000) 91 ; CHECK-NEXT: {{ $}} 92 ; CHECK-NEXT: [[LFSU:%[0-9]+]]:f4rc, [[LFSU1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[ADDI8_]] :: (load (s32) from %ir.3) 93 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LFSU1]] 94 ; CHECK-NEXT: BDZ8 %bb.17, implicit-def $ctr8, implicit $ctr8 95 ; CHECK-NEXT: B %bb.4 96 ; CHECK-NEXT: {{ $}} 97 ; CHECK-NEXT: bb.4.for.body: 98 ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.16(0x40000000) 99 ; CHECK-NEXT: {{ $}} 100 ; CHECK-NEXT: [[LFSU2:%[0-9]+]]:f4rc, [[LFSU3:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[COPY3]] :: (load unknown-size from %ir.3, align 4) 101 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LFSU3]] 102 ; CHECK-NEXT: BDZ8 %bb.16, implicit-def $ctr8, implicit $ctr8 103 ; CHECK-NEXT: B %bb.5 104 ; CHECK-NEXT: {{ $}} 105 ; CHECK-NEXT: bb.5.for.body: 106 ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.15(0x40000000) 107 ; CHECK-NEXT: {{ $}} 108 ; CHECK-NEXT: [[XSADDSP:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[LFSU]], [[LFSU]] 109 ; CHECK-NEXT: [[LFSU4:%[0-9]+]]:f4rc, [[LFSU5:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[COPY4]] :: (load unknown-size from %ir.3, align 4) 110 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LFSU5]] 111 ; CHECK-NEXT: BDZ8 %bb.15, implicit-def $ctr8, implicit $ctr8 112 ; CHECK-NEXT: B %bb.6 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: bb.6.for.body: 115 ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.14(0x40000000) 116 ; CHECK-NEXT: {{ $}} 117 ; CHECK-NEXT: [[XSADDSP1:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[LFSU2]], [[LFSU2]] 118 ; CHECK-NEXT: [[LFSU6:%[0-9]+]]:f4rc, [[LFSU7:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[COPY5]] :: (load unknown-size from %ir.3, align 4) 119 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LFSU7]] 120 ; CHECK-NEXT: BDZ8 %bb.14, implicit-def $ctr8, implicit $ctr8 121 ; CHECK-NEXT: B %bb.7 122 ; CHECK-NEXT: {{ $}} 123 ; CHECK-NEXT: bb.7.for.body: 124 ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.13(0x40000000) 125 ; CHECK-NEXT: {{ $}} 126 ; CHECK-NEXT: [[XSADDSP2:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[LFSU]], [[XSADDSP]] 127 ; CHECK-NEXT: [[XSADDSP3:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[LFSU4]], [[LFSU4]] 128 ; CHECK-NEXT: [[LFSU8:%[0-9]+]]:f4rc, [[LFSU9:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[COPY6]] :: (load unknown-size from %ir.3, align 4) 129 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LFSU9]] 130 ; CHECK-NEXT: BDZ8 %bb.13, implicit-def $ctr8, implicit $ctr8 131 ; CHECK-NEXT: B %bb.8 132 ; CHECK-NEXT: {{ $}} 133 ; CHECK-NEXT: bb.8.for.body: 134 ; CHECK-NEXT: successors: %bb.9(0x40000000), %bb.12(0x40000000) 135 ; CHECK-NEXT: {{ $}} 136 ; CHECK-NEXT: [[XSADDSP4:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[LFSU2]], [[XSADDSP1]] 137 ; CHECK-NEXT: [[XSADDSP5:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[LFSU6]], [[LFSU6]] 138 ; CHECK-NEXT: [[LFSU10:%[0-9]+]]:f4rc, [[LFSU11:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[COPY7]] :: (load unknown-size from %ir.3, align 4) 139 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LFSU11]] 140 ; CHECK-NEXT: BDZ8 %bb.12, implicit-def $ctr8, implicit $ctr8 141 ; CHECK-NEXT: B %bb.9 142 ; CHECK-NEXT: {{ $}} 143 ; CHECK-NEXT: bb.9.for.body: 144 ; CHECK-NEXT: successors: %bb.10(0x80000000), %bb.11(0x00000000) 145 ; CHECK-NEXT: {{ $}} 146 ; CHECK-NEXT: [[XSADDSP6:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[LFSU4]], [[XSADDSP3]] 147 ; CHECK-NEXT: [[XSADDSP7:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[LFSU8]], [[LFSU8]] 148 ; CHECK-NEXT: [[LFSU12:%[0-9]+]]:f4rc, [[LFSU13:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[COPY8]] :: (load unknown-size from %ir.3, align 4) 149 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:g8rc = COPY [[LFSU13]] 150 ; CHECK-NEXT: BDZ8 %bb.11, implicit-def $ctr8, implicit $ctr8 151 ; CHECK-NEXT: B %bb.10 152 ; CHECK-NEXT: {{ $}} 153 ; CHECK-NEXT: bb.10.for.body: 154 ; CHECK-NEXT: successors: %bb.10(0x7c000000), %bb.11(0x04000000) 155 ; CHECK-NEXT: {{ $}} 156 ; CHECK-NEXT: [[PHI:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[COPY9]], %bb.9, %50, %bb.10 157 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.9, %47, %bb.10 158 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:f4rc = PHI [[LFSU12]], %bb.9, %45, %bb.10 159 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:f4rc = PHI [[LFSU10]], %bb.9, [[PHI2]], %bb.10 160 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:f4rc = PHI [[LFSU8]], %bb.9, [[PHI3]], %bb.10 161 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:f4rc = PHI [[LFSU6]], %bb.9, [[PHI4]], %bb.10 162 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:vssrc = PHI [[XSADDSP7]], %bb.9, %48, %bb.10 163 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:vssrc = PHI [[XSADDSP5]], %bb.9, [[PHI6]], %bb.10 164 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:f4rc = PHI [[XSADDSP6]], %bb.9, %49, %bb.10 165 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:f4rc = PHI [[XSADDSP4]], %bb.9, [[PHI8]], %bb.10 166 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:f4rc = PHI [[XSADDSP2]], %bb.9, [[PHI9]], %bb.10 167 ; CHECK-NEXT: [[STFSU:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[PHI10]], 4, [[PHI1]] :: (store (s32) into %ir.2) 168 ; CHECK-NEXT: [[LFSU14:%[0-9]+]]:f4rc, [[LFSU15:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSU 4, [[PHI]] :: (load unknown-size from %ir.3, align 4) 169 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:g8rc = COPY [[STFSU]] 170 ; CHECK-NEXT: [[XSADDSP8:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[PHI3]], [[PHI3]] 171 ; CHECK-NEXT: [[XSADDSP9:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[PHI5]], [[PHI7]] 172 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:g8rc = COPY [[LFSU15]] 173 ; CHECK-NEXT: BDNZ8 %bb.10, implicit-def $ctr8, implicit $ctr8 174 ; CHECK-NEXT: B %bb.11 175 ; CHECK-NEXT: {{ $}} 176 ; CHECK-NEXT: bb.11: 177 ; CHECK-NEXT: successors: %bb.12(0x80000000) 178 ; CHECK-NEXT: {{ $}} 179 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.9, [[COPY10]], %bb.10 180 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:f4rc = PHI [[LFSU12]], %bb.9, [[LFSU14]], %bb.10 181 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:f4rc = PHI [[LFSU10]], %bb.9, [[PHI2]], %bb.10 182 ; CHECK-NEXT: [[PHI14:%[0-9]+]]:f4rc = PHI [[LFSU8]], %bb.9, [[PHI3]], %bb.10 183 ; CHECK-NEXT: [[PHI15:%[0-9]+]]:f4rc = PHI [[LFSU6]], %bb.9, [[PHI4]], %bb.10 184 ; CHECK-NEXT: [[PHI16:%[0-9]+]]:vssrc = PHI [[XSADDSP7]], %bb.9, [[XSADDSP8]], %bb.10 185 ; CHECK-NEXT: [[PHI17:%[0-9]+]]:vssrc = PHI [[XSADDSP5]], %bb.9, [[PHI6]], %bb.10 186 ; CHECK-NEXT: [[PHI18:%[0-9]+]]:f4rc = PHI [[XSADDSP6]], %bb.9, [[XSADDSP9]], %bb.10 187 ; CHECK-NEXT: [[PHI19:%[0-9]+]]:f4rc = PHI [[XSADDSP4]], %bb.9, [[PHI8]], %bb.10 188 ; CHECK-NEXT: [[PHI20:%[0-9]+]]:f4rc = PHI [[XSADDSP2]], %bb.9, [[PHI9]], %bb.10 189 ; CHECK-NEXT: [[STFSU1:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[PHI20]], 4, [[PHI11]] :: (store unknown-size into %ir.2, align 4) 190 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:g8rc = COPY [[STFSU1]] 191 ; CHECK-NEXT: {{ $}} 192 ; CHECK-NEXT: bb.12: 193 ; CHECK-NEXT: successors: %bb.13(0x80000000) 194 ; CHECK-NEXT: {{ $}} 195 ; CHECK-NEXT: [[PHI21:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.8, [[COPY12]], %bb.11 196 ; CHECK-NEXT: [[PHI22:%[0-9]+]]:f4rc = PHI [[LFSU10]], %bb.8, [[PHI12]], %bb.11 197 ; CHECK-NEXT: [[PHI23:%[0-9]+]]:f4rc = PHI [[LFSU8]], %bb.8, [[PHI13]], %bb.11 198 ; CHECK-NEXT: [[PHI24:%[0-9]+]]:f4rc = PHI [[LFSU6]], %bb.8, [[PHI14]], %bb.11 199 ; CHECK-NEXT: [[PHI25:%[0-9]+]]:f4rc = PHI [[LFSU4]], %bb.8, [[PHI15]], %bb.11 200 ; CHECK-NEXT: [[PHI26:%[0-9]+]]:vssrc = PHI [[XSADDSP5]], %bb.8, [[PHI16]], %bb.11 201 ; CHECK-NEXT: [[PHI27:%[0-9]+]]:vssrc = PHI [[XSADDSP3]], %bb.8, [[PHI17]], %bb.11 202 ; CHECK-NEXT: [[PHI28:%[0-9]+]]:f4rc = PHI [[XSADDSP4]], %bb.8, [[PHI18]], %bb.11 203 ; CHECK-NEXT: [[PHI29:%[0-9]+]]:f4rc = PHI [[XSADDSP2]], %bb.8, [[PHI19]], %bb.11 204 ; CHECK-NEXT: [[STFSU2:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[PHI29]], 4, [[PHI21]] :: (store unknown-size into %ir.2, align 4) 205 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:g8rc = COPY [[STFSU2]] 206 ; CHECK-NEXT: {{ $}} 207 ; CHECK-NEXT: bb.13: 208 ; CHECK-NEXT: successors: %bb.14(0x80000000) 209 ; CHECK-NEXT: {{ $}} 210 ; CHECK-NEXT: [[PHI30:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.7, [[COPY13]], %bb.12 211 ; CHECK-NEXT: [[PHI31:%[0-9]+]]:f4rc = PHI [[LFSU8]], %bb.7, [[PHI22]], %bb.12 212 ; CHECK-NEXT: [[PHI32:%[0-9]+]]:f4rc = PHI [[LFSU6]], %bb.7, [[PHI23]], %bb.12 213 ; CHECK-NEXT: [[PHI33:%[0-9]+]]:f4rc = PHI [[LFSU4]], %bb.7, [[PHI24]], %bb.12 214 ; CHECK-NEXT: [[PHI34:%[0-9]+]]:f4rc = PHI [[LFSU2]], %bb.7, [[PHI25]], %bb.12 215 ; CHECK-NEXT: [[PHI35:%[0-9]+]]:vssrc = PHI [[XSADDSP3]], %bb.7, [[PHI26]], %bb.12 216 ; CHECK-NEXT: [[PHI36:%[0-9]+]]:vssrc = PHI [[XSADDSP1]], %bb.7, [[PHI27]], %bb.12 217 ; CHECK-NEXT: [[PHI37:%[0-9]+]]:f4rc = PHI [[XSADDSP2]], %bb.7, [[PHI28]], %bb.12 218 ; CHECK-NEXT: [[STFSU3:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[PHI37]], 4, [[PHI30]] :: (store unknown-size into %ir.2, align 4) 219 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:g8rc = COPY [[STFSU3]] 220 ; CHECK-NEXT: {{ $}} 221 ; CHECK-NEXT: bb.14: 222 ; CHECK-NEXT: successors: %bb.15(0x80000000) 223 ; CHECK-NEXT: {{ $}} 224 ; CHECK-NEXT: [[PHI38:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.6, [[COPY14]], %bb.13 225 ; CHECK-NEXT: [[PHI39:%[0-9]+]]:f4rc = PHI [[LFSU6]], %bb.6, [[PHI31]], %bb.13 226 ; CHECK-NEXT: [[PHI40:%[0-9]+]]:f4rc = PHI [[LFSU4]], %bb.6, [[PHI32]], %bb.13 227 ; CHECK-NEXT: [[PHI41:%[0-9]+]]:f4rc = PHI [[LFSU2]], %bb.6, [[PHI33]], %bb.13 228 ; CHECK-NEXT: [[PHI42:%[0-9]+]]:f4rc = PHI [[LFSU]], %bb.6, [[PHI34]], %bb.13 229 ; CHECK-NEXT: [[PHI43:%[0-9]+]]:vssrc = PHI [[XSADDSP1]], %bb.6, [[PHI35]], %bb.13 230 ; CHECK-NEXT: [[PHI44:%[0-9]+]]:vssrc = PHI [[XSADDSP]], %bb.6, [[PHI36]], %bb.13 231 ; CHECK-NEXT: [[XSADDSP10:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[PHI42]], [[PHI44]] 232 ; CHECK-NEXT: [[STFSU4:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[XSADDSP10]], 4, [[PHI38]] :: (store unknown-size into %ir.2, align 4) 233 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:g8rc = COPY [[STFSU4]] 234 ; CHECK-NEXT: {{ $}} 235 ; CHECK-NEXT: bb.15: 236 ; CHECK-NEXT: successors: %bb.16(0x80000000) 237 ; CHECK-NEXT: {{ $}} 238 ; CHECK-NEXT: [[PHI45:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.5, [[COPY15]], %bb.14 239 ; CHECK-NEXT: [[PHI46:%[0-9]+]]:f4rc = PHI [[LFSU4]], %bb.5, [[PHI39]], %bb.14 240 ; CHECK-NEXT: [[PHI47:%[0-9]+]]:f4rc = PHI [[LFSU2]], %bb.5, [[PHI40]], %bb.14 241 ; CHECK-NEXT: [[PHI48:%[0-9]+]]:f4rc = PHI [[LFSU]], %bb.5, [[PHI41]], %bb.14 242 ; CHECK-NEXT: [[PHI49:%[0-9]+]]:vssrc = PHI [[XSADDSP]], %bb.5, [[PHI43]], %bb.14 243 ; CHECK-NEXT: [[XSADDSP11:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[PHI48]], [[PHI49]] 244 ; CHECK-NEXT: [[STFSU5:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[XSADDSP11]], 4, [[PHI45]] :: (store unknown-size into %ir.2, align 4) 245 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:g8rc = COPY [[STFSU5]] 246 ; CHECK-NEXT: {{ $}} 247 ; CHECK-NEXT: bb.16: 248 ; CHECK-NEXT: successors: %bb.17(0x80000000) 249 ; CHECK-NEXT: {{ $}} 250 ; CHECK-NEXT: [[PHI50:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.4, [[COPY16]], %bb.15 251 ; CHECK-NEXT: [[PHI51:%[0-9]+]]:f4rc = PHI [[LFSU2]], %bb.4, [[PHI46]], %bb.15 252 ; CHECK-NEXT: [[PHI52:%[0-9]+]]:f4rc = PHI [[LFSU]], %bb.4, [[PHI47]], %bb.15 253 ; CHECK-NEXT: [[XSADDSP12:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[PHI52]], [[PHI52]] 254 ; CHECK-NEXT: [[XSADDSP13:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[PHI52]], [[XSADDSP12]] 255 ; CHECK-NEXT: [[STFSU6:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[XSADDSP13]], 4, [[PHI50]] :: (store unknown-size into %ir.2, align 4) 256 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:g8rc = COPY [[STFSU6]] 257 ; CHECK-NEXT: {{ $}} 258 ; CHECK-NEXT: bb.17: 259 ; CHECK-NEXT: successors: %bb.1(0x80000000) 260 ; CHECK-NEXT: {{ $}} 261 ; CHECK-NEXT: [[PHI53:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.3, [[COPY17]], %bb.16 262 ; CHECK-NEXT: [[PHI54:%[0-9]+]]:f4rc = PHI [[LFSU]], %bb.3, [[PHI51]], %bb.16 263 ; CHECK-NEXT: [[XSADDSP14:%[0-9]+]]:vssrc = nofpexcept XSADDSP [[PHI54]], [[PHI54]] 264 ; CHECK-NEXT: [[XSADDSP15:%[0-9]+]]:f4rc = nofpexcept XSADDSP [[PHI54]], [[XSADDSP14]] 265 ; CHECK-NEXT: [[STFSU7:%[0-9]+]]:g8rc_and_g8rc_nox0 = STFSU [[XSADDSP15]], 4, [[PHI53]] :: (store unknown-size into %ir.2, align 4) 266 ; CHECK-NEXT: B %bb.1 267 bb.0.entry: 268 liveins: $x3, $x4, $x5 269 270 %8:g8rc = COPY $x5 271 %7:g8rc_and_g8rc_nox0 = COPY $x4 272 %6:g8rc_and_g8rc_nox0 = COPY $x3 273 %9:g8rc = RLDICL %8, 0, 32 274 %0:g8rc = ADDI8 %7, -4 275 %1:g8rc = ADDI8 %6, -4 276 MTCTR8loop killed %9, implicit-def dead $ctr8 277 B %bb.2 278 279 bb.1.for.cond.cleanup: 280 BLR8 implicit $lr8, implicit $rm 281 282 bb.2.for.body: 283 successors: %bb.2(0x7c000000), %bb.1(0x04000000) 284 285 %2:g8rc_and_g8rc_nox0 = PHI %0, %bb.0, %5, %bb.2 286 %3:g8rc_and_g8rc_nox0 = PHI %1, %bb.0, %4, %bb.2 287 %10:f4rc, %11:g8rc_and_g8rc_nox0 = LFSU 4, %2 :: (load (s32) from %ir.3) 288 %12:vssrc = nofpexcept XSADDSP %10, %10 289 %13:f4rc = nofpexcept XSADDSP %10, killed %12 290 %14:g8rc_and_g8rc_nox0 = STFSU killed %13, 4, %3 :: (store (s32) into %ir.2) 291 %4:g8rc = COPY %14 292 %5:g8rc = COPY %11 293 BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8 294 B %bb.1 295 296... 297