xref: /llvm-project/llvm/test/CodeGen/PowerPC/sms-grp-order.ll (revision 5403c59c608c08c8ecd4303763f08eb046eb5e4d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
3; RUN:       -mcpu=pwr9 --ppc-enable-pipeliner | FileCheck %s
4
5define void @lame_encode_buffer_interleaved() local_unnamed_addr {
6; CHECK-LABEL: lame_encode_buffer_interleaved:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    lha 3, 0(3)
9; CHECK-NEXT:    li 5, 1
10; CHECK-NEXT:    lhz 4, 0(0)
11; CHECK-NEXT:    rldic 5, 5, 62, 1
12; CHECK-NEXT:    mtctr 5
13; CHECK-NEXT:    srawi 3, 3, 1
14; CHECK-NEXT:    addze 3, 3
15; CHECK-NEXT:    .p2align 4
16; CHECK-NEXT:  .LBB0_1:
17; CHECK-NEXT:    extsh 4, 4
18; CHECK-NEXT:    srawi 4, 4, 1
19; CHECK-NEXT:    addze 4, 4
20; CHECK-NEXT:    bdnz .LBB0_1
21; CHECK-NEXT:  # %bb.2:
22; CHECK-NEXT:    sth 4, 0(0)
23; CHECK-NEXT:    sth 3, 0(3)
24; CHECK-NEXT:    blr
25  br label %1
26
271:                                                ; preds = %1, %0
28  %2 = phi i64 [ 0, %0 ], [ %13, %1 ]
29  %3 = load i16, ptr null, align 2
30  %4 = load i16, ptr undef, align 2
31  %5 = sext i16 %3 to i32
32  %6 = sext i16 %4 to i32
33  %7 = add nsw i32 0, %5
34  %8 = add nsw i32 0, %6
35  %9 = sdiv i32 %7, 2
36  %10 = sdiv i32 %8, 2
37  %11 = trunc i32 %9 to i16
38  %12 = trunc i32 %10 to i16
39  store i16 %11, ptr null, align 2
40  store i16 %12, ptr undef, align 2
41  %13 = add i64 %2, 4
42  %14 = icmp eq i64 %13, 0
43  br i1 %14, label %15, label %1
44
4515:                                               ; preds = %1
46  ret void
47}
48