xref: /llvm-project/llvm/test/CodeGen/PowerPC/sh-overflow.mir (revision c7be06797436f558e1c925fae1aba8629cd1f5bf) 
1# RUN: llc -O3 -mtriple=powerpc64le-unknown-linux-gnu -start-after ppc-mi-peepholes -ppc-late-peephole -ppc-asm-full-reg-names -verify-machineinstrs %s -o - | FileCheck %s
2
3---
4name:            special_right_shift32_0
5alignment:       2
6tracksRegLiveness: true
7registers:
8  - { id: 0, class: gprc }
9  - { id: 1, class: gprc }
10  - { id: 2, class: gprc }
11liveins:
12  - { reg: '$r3', virtual-reg: '%0' }
13machineFunctionInfo: {}
14body:             |
15  bb.0.entry:
16    liveins: $r3
17
18    ; Ensure we do not attempt to transform this into srwi $r3, $r3, 0 in the
19    ; form specified by ISA 3.0b (rlwinm $r3, $r3, 32 - 0, 0, 31)
20
21    ; CHECK-LABEL: special_right_shift32_0:
22    ; CHECK:         slwi r[[#]], r[[#]], 0
23
24    %0:gprc = COPY killed $r3
25    %1:gprc = LI 0
26    %2:gprc = SRW killed %0, killed %1
27    $r3 = COPY killed %2
28    BLR implicit $lr, implicit $rm, implicit killed $r3
29
30...
31---
32name:            special_right_shift64_0
33alignment:       2
34tracksRegLiveness: true
35registers:
36  - { id: 0, class: g8rc }
37  - { id: 1, class: gprc }
38  - { id: 2, class: g8rc }
39liveins:
40  - { reg: '$x3', virtual-reg: '%0' }
41machineFunctionInfo: {}
42body:             |
43  bb.0.entry:
44    liveins: $x3
45
46    ; Ensure we do not attempt to transform this into srdi $r3, $r3, 0 in the
47    ; form specified by ISA 3.0b (rldicl $r3, $r3, 64 - 0, 0)
48
49    ; CHECK-LABEL: special_right_shift64_0:
50    ; CHECK:         rotldi r[[#]], r[[#]], 0
51
52    %0:g8rc = COPY killed $x3
53    %1:gprc = LI 0
54    %2:g8rc = SRD killed %0, killed %1
55    $x3 = COPY killed %2
56    BLR8 implicit $lr8, implicit $rm, implicit killed $x3
57
58...
59