1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true | FileCheck %s 3 4define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { 5; CHECK-LABEL: all_bits_clear: 6; CHECK: # %bb.0: 7; CHECK-NEXT: or 3, 3, 4 8; CHECK-NEXT: cntlzw 3, 3 9; CHECK-NEXT: srwi 3, 3, 5 10; CHECK-NEXT: blr 11 %a = icmp eq i32 %P, 0 12 %b = icmp eq i32 %Q, 0 13 %c = and i1 %a, %b 14 ret i1 %c 15} 16 17define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) { 18; CHECK-LABEL: all_sign_bits_clear: 19; CHECK: # %bb.0: 20; CHECK-NEXT: or 3, 3, 4 21; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 22; CHECK-NEXT: xori 3, 3, 1 23; CHECK-NEXT: blr 24 %a = icmp sgt i32 %P, -1 25 %b = icmp sgt i32 %Q, -1 26 %c = and i1 %a, %b 27 ret i1 %c 28} 29 30define zeroext i1 @all_bits_set(i32 %P, i32 %Q) { 31; CHECK-LABEL: all_bits_set: 32; CHECK: # %bb.0: 33; CHECK-NEXT: and 3, 3, 4 34; CHECK-NEXT: li 4, -1 35; CHECK-NEXT: xor 3, 3, 4 36; CHECK-NEXT: cntlzw 3, 3 37; CHECK-NEXT: srwi 3, 3, 5 38; CHECK-NEXT: blr 39 %a = icmp eq i32 %P, -1 40 %b = icmp eq i32 %Q, -1 41 %c = and i1 %a, %b 42 ret i1 %c 43} 44 45define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) { 46; CHECK-LABEL: all_sign_bits_set: 47; CHECK: # %bb.0: 48; CHECK-NEXT: and 3, 3, 4 49; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 50; CHECK-NEXT: blr 51 %a = icmp slt i32 %P, 0 52 %b = icmp slt i32 %Q, 0 53 %c = and i1 %a, %b 54 ret i1 %c 55} 56 57define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { 58; CHECK-LABEL: any_bits_set: 59; CHECK: # %bb.0: 60; CHECK-NEXT: or 3, 3, 4 61; CHECK-NEXT: cntlzw 3, 3 62; CHECK-NEXT: srwi 3, 3, 5 63; CHECK-NEXT: xori 3, 3, 1 64; CHECK-NEXT: blr 65 %a = icmp ne i32 %P, 0 66 %b = icmp ne i32 %Q, 0 67 %c = or i1 %a, %b 68 ret i1 %c 69} 70 71define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { 72; CHECK-LABEL: any_sign_bits_set: 73; CHECK: # %bb.0: 74; CHECK-NEXT: or 3, 3, 4 75; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 76; CHECK-NEXT: blr 77 %a = icmp slt i32 %P, 0 78 %b = icmp slt i32 %Q, 0 79 %c = or i1 %a, %b 80 ret i1 %c 81} 82 83define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { 84; CHECK-LABEL: any_bits_clear: 85; CHECK: # %bb.0: 86; CHECK-NEXT: and 3, 3, 4 87; CHECK-NEXT: li 4, -1 88; CHECK-NEXT: xor 3, 3, 4 89; CHECK-NEXT: cntlzw 3, 3 90; CHECK-NEXT: srwi 3, 3, 5 91; CHECK-NEXT: xori 3, 3, 1 92; CHECK-NEXT: blr 93 %a = icmp ne i32 %P, -1 94 %b = icmp ne i32 %Q, -1 95 %c = or i1 %a, %b 96 ret i1 %c 97} 98 99define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { 100; CHECK-LABEL: any_sign_bits_clear: 101; CHECK: # %bb.0: 102; CHECK-NEXT: and 3, 3, 4 103; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 104; CHECK-NEXT: xori 3, 3, 1 105; CHECK-NEXT: blr 106 %a = icmp sgt i32 %P, -1 107 %b = icmp sgt i32 %Q, -1 108 %c = or i1 %a, %b 109 ret i1 %c 110} 111 112; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0 113define i32 @all_bits_clear_branch(ptr %P, ptr %Q) { 114; CHECK-LABEL: all_bits_clear_branch: 115; CHECK: # %bb.0: # %entry 116; CHECK-NEXT: or. 3, 3, 4 117; CHECK-NEXT: bne 0, .LBB8_2 118; CHECK-NEXT: # %bb.1: # %bb1 119; CHECK-NEXT: li 3, 4 120; CHECK-NEXT: blr 121; CHECK-NEXT: .LBB8_2: # %return 122; CHECK-NEXT: li 3, 192 123; CHECK-NEXT: blr 124entry: 125 %a = icmp eq ptr %P, null 126 %b = icmp eq ptr %Q, null 127 %c = and i1 %a, %b 128 br i1 %c, label %bb1, label %return 129 130bb1: 131 ret i32 4 132 133return: 134 ret i32 192 135} 136 137define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) { 138; CHECK-LABEL: all_sign_bits_clear_branch: 139; CHECK: # %bb.0: # %entry 140; CHECK-NEXT: or 3, 3, 4 141; CHECK-NEXT: cmpwi 3, 0 142; CHECK-NEXT: blt 0, .LBB9_2 143; CHECK-NEXT: # %bb.1: # %bb1 144; CHECK-NEXT: li 3, 4 145; CHECK-NEXT: blr 146; CHECK-NEXT: .LBB9_2: # %return 147; CHECK-NEXT: li 3, 192 148; CHECK-NEXT: blr 149entry: 150 %a = icmp sgt i32 %P, -1 151 %b = icmp sgt i32 %Q, -1 152 %c = and i1 %a, %b 153 br i1 %c, label %bb1, label %return 154 155bb1: 156 ret i32 4 157 158return: 159 ret i32 192 160} 161 162define i32 @all_bits_set_branch(i32 %P, i32 %Q) { 163; CHECK-LABEL: all_bits_set_branch: 164; CHECK: # %bb.0: # %entry 165; CHECK-NEXT: and 3, 3, 4 166; CHECK-NEXT: cmpwi 3, -1 167; CHECK-NEXT: bne 0, .LBB10_2 168; CHECK-NEXT: # %bb.1: # %bb1 169; CHECK-NEXT: li 3, 4 170; CHECK-NEXT: blr 171; CHECK-NEXT: .LBB10_2: # %return 172; CHECK-NEXT: li 3, 192 173; CHECK-NEXT: blr 174entry: 175 %a = icmp eq i32 %P, -1 176 %b = icmp eq i32 %Q, -1 177 %c = and i1 %a, %b 178 br i1 %c, label %bb1, label %return 179 180bb1: 181 ret i32 4 182 183return: 184 ret i32 192 185} 186 187define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) { 188; CHECK-LABEL: all_sign_bits_set_branch: 189; CHECK: # %bb.0: # %entry 190; CHECK-NEXT: and 3, 3, 4 191; CHECK-NEXT: cmpwi 3, -1 192; CHECK-NEXT: bgt 0, .LBB11_2 193; CHECK-NEXT: # %bb.1: # %bb1 194; CHECK-NEXT: li 3, 4 195; CHECK-NEXT: blr 196; CHECK-NEXT: .LBB11_2: # %return 197; CHECK-NEXT: li 3, 192 198; CHECK-NEXT: blr 199entry: 200 %a = icmp slt i32 %P, 0 201 %b = icmp slt i32 %Q, 0 202 %c = and i1 %a, %b 203 br i1 %c, label %bb1, label %return 204 205bb1: 206 ret i32 4 207 208return: 209 ret i32 192 210} 211 212; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0 213define i32 @any_bits_set_branch(ptr %P, ptr %Q) { 214; CHECK-LABEL: any_bits_set_branch: 215; CHECK: # %bb.0: # %entry 216; CHECK-NEXT: or. 3, 3, 4 217; CHECK-NEXT: beq 0, .LBB12_2 218; CHECK-NEXT: # %bb.1: # %bb1 219; CHECK-NEXT: li 3, 4 220; CHECK-NEXT: blr 221; CHECK-NEXT: .LBB12_2: # %return 222; CHECK-NEXT: li 3, 192 223; CHECK-NEXT: blr 224entry: 225 %a = icmp ne ptr %P, null 226 %b = icmp ne ptr %Q, null 227 %c = or i1 %a, %b 228 br i1 %c, label %bb1, label %return 229 230bb1: 231 ret i32 4 232 233return: 234 ret i32 192 235} 236 237define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) { 238; CHECK-LABEL: any_sign_bits_set_branch: 239; CHECK: # %bb.0: # %entry 240; CHECK-NEXT: or 3, 3, 4 241; CHECK-NEXT: cmpwi 3, -1 242; CHECK-NEXT: bgt 0, .LBB13_2 243; CHECK-NEXT: # %bb.1: # %bb1 244; CHECK-NEXT: li 3, 4 245; CHECK-NEXT: blr 246; CHECK-NEXT: .LBB13_2: # %return 247; CHECK-NEXT: li 3, 192 248; CHECK-NEXT: blr 249entry: 250 %a = icmp slt i32 %P, 0 251 %b = icmp slt i32 %Q, 0 252 %c = or i1 %a, %b 253 br i1 %c, label %bb1, label %return 254 255bb1: 256 ret i32 4 257 258return: 259 ret i32 192 260} 261 262define i32 @any_bits_clear_branch(i32 %P, i32 %Q) { 263; CHECK-LABEL: any_bits_clear_branch: 264; CHECK: # %bb.0: # %entry 265; CHECK-NEXT: and 3, 3, 4 266; CHECK-NEXT: cmpwi 3, -1 267; CHECK-NEXT: beq 0, .LBB14_2 268; CHECK-NEXT: # %bb.1: # %bb1 269; CHECK-NEXT: li 3, 4 270; CHECK-NEXT: blr 271; CHECK-NEXT: .LBB14_2: # %return 272; CHECK-NEXT: li 3, 192 273; CHECK-NEXT: blr 274entry: 275 %a = icmp ne i32 %P, -1 276 %b = icmp ne i32 %Q, -1 277 %c = or i1 %a, %b 278 br i1 %c, label %bb1, label %return 279 280bb1: 281 ret i32 4 282 283return: 284 ret i32 192 285} 286 287define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) { 288; CHECK-LABEL: any_sign_bits_clear_branch: 289; CHECK: # %bb.0: # %entry 290; CHECK-NEXT: and 3, 3, 4 291; CHECK-NEXT: cmpwi 3, 0 292; CHECK-NEXT: blt 0, .LBB15_2 293; CHECK-NEXT: # %bb.1: # %bb1 294; CHECK-NEXT: li 3, 4 295; CHECK-NEXT: blr 296; CHECK-NEXT: .LBB15_2: # %return 297; CHECK-NEXT: li 3, 192 298; CHECK-NEXT: blr 299entry: 300 %a = icmp sgt i32 %P, -1 301 %b = icmp sgt i32 %Q, -1 302 %c = or i1 %a, %b 303 br i1 %c, label %bb1, label %return 304 305bb1: 306 ret i32 4 307 308return: 309 ret i32 192 310} 311 312define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { 313; CHECK-LABEL: all_bits_clear_vec: 314; CHECK: # %bb.0: 315; CHECK-NEXT: xxlor 34, 34, 35 316; CHECK-NEXT: xxlxor 35, 35, 35 317; CHECK-NEXT: vcmpequw 2, 2, 3 318; CHECK-NEXT: blr 319 %a = icmp eq <4 x i32> %P, zeroinitializer 320 %b = icmp eq <4 x i32> %Q, zeroinitializer 321 %c = and <4 x i1> %a, %b 322 ret <4 x i1> %c 323} 324 325define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { 326; CHECK-LABEL: all_sign_bits_clear_vec: 327; CHECK: # %bb.0: 328; CHECK-NEXT: xxlor 34, 34, 35 329; CHECK-NEXT: xxleqv 35, 35, 35 330; CHECK-NEXT: vcmpgtsw 2, 2, 3 331; CHECK-NEXT: blr 332 %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 333 %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 334 %c = and <4 x i1> %a, %b 335 ret <4 x i1> %c 336} 337 338define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { 339; CHECK-LABEL: all_bits_set_vec: 340; CHECK: # %bb.0: 341; CHECK-NEXT: xxland 34, 34, 35 342; CHECK-NEXT: xxleqv 35, 35, 35 343; CHECK-NEXT: vcmpequw 2, 2, 3 344; CHECK-NEXT: blr 345 %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 346 %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 347 %c = and <4 x i1> %a, %b 348 ret <4 x i1> %c 349} 350 351define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { 352; CHECK-LABEL: all_sign_bits_set_vec: 353; CHECK: # %bb.0: 354; CHECK-NEXT: xxland 34, 34, 35 355; CHECK-NEXT: xxlxor 35, 35, 35 356; CHECK-NEXT: vcmpgtsw 2, 3, 2 357; CHECK-NEXT: blr 358 %a = icmp slt <4 x i32> %P, zeroinitializer 359 %b = icmp slt <4 x i32> %Q, zeroinitializer 360 %c = and <4 x i1> %a, %b 361 ret <4 x i1> %c 362} 363 364define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { 365; CHECK-LABEL: any_bits_set_vec: 366; CHECK: # %bb.0: 367; CHECK-NEXT: xxlor 34, 34, 35 368; CHECK-NEXT: xxlxor 35, 35, 35 369; CHECK-NEXT: vcmpequw 2, 2, 3 370; CHECK-NEXT: xxlnor 34, 34, 34 371; CHECK-NEXT: blr 372 %a = icmp ne <4 x i32> %P, zeroinitializer 373 %b = icmp ne <4 x i32> %Q, zeroinitializer 374 %c = or <4 x i1> %a, %b 375 ret <4 x i1> %c 376} 377 378define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { 379; CHECK-LABEL: any_sign_bits_set_vec: 380; CHECK: # %bb.0: 381; CHECK-NEXT: xxlor 34, 34, 35 382; CHECK-NEXT: xxlxor 35, 35, 35 383; CHECK-NEXT: vcmpgtsw 2, 3, 2 384; CHECK-NEXT: blr 385 %a = icmp slt <4 x i32> %P, zeroinitializer 386 %b = icmp slt <4 x i32> %Q, zeroinitializer 387 %c = or <4 x i1> %a, %b 388 ret <4 x i1> %c 389} 390 391define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { 392; CHECK-LABEL: any_bits_clear_vec: 393; CHECK: # %bb.0: 394; CHECK-NEXT: xxland 34, 34, 35 395; CHECK-NEXT: xxleqv 35, 35, 35 396; CHECK-NEXT: vcmpequw 2, 2, 3 397; CHECK-NEXT: xxlnor 34, 34, 34 398; CHECK-NEXT: blr 399 %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 400 %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 401 %c = or <4 x i1> %a, %b 402 ret <4 x i1> %c 403} 404 405define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { 406; CHECK-LABEL: any_sign_bits_clear_vec: 407; CHECK: # %bb.0: 408; CHECK-NEXT: xxland 34, 34, 35 409; CHECK-NEXT: xxleqv 35, 35, 35 410; CHECK-NEXT: vcmpgtsw 2, 2, 3 411; CHECK-NEXT: blr 412 %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 413 %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 414 %c = or <4 x i1> %a, %b 415 ret <4 x i1> %c 416} 417 418define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { 419; CHECK-LABEL: ne_neg1_and_ne_zero: 420; CHECK: # %bb.0: 421; CHECK-NEXT: addi 3, 3, 1 422; CHECK-NEXT: li 4, 1 423; CHECK-NEXT: subfic 3, 3, 1 424; CHECK-NEXT: subfe 3, 4, 4 425; CHECK-NEXT: neg 3, 3 426; CHECK-NEXT: blr 427 %cmp1 = icmp ne i64 %x, -1 428 %cmp2 = icmp ne i64 %x, 0 429 %and = and i1 %cmp1, %cmp2 430 ret i1 %and 431} 432 433; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401 434 435define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) { 436; CHECK-LABEL: and_eq: 437; CHECK: # %bb.0: 438; CHECK-NEXT: xor 3, 3, 4 439; CHECK-NEXT: xor 4, 5, 6 440; CHECK-NEXT: or 3, 3, 4 441; CHECK-NEXT: cntlzw 3, 3 442; CHECK-NEXT: srwi 3, 3, 5 443; CHECK-NEXT: blr 444 %cmp1 = icmp eq i16 %a, %b 445 %cmp2 = icmp eq i16 %c, %d 446 %and = and i1 %cmp1, %cmp2 447 ret i1 %and 448} 449 450define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { 451; CHECK-LABEL: or_ne: 452; CHECK: # %bb.0: 453; CHECK-NEXT: xor 3, 3, 4 454; CHECK-NEXT: xor 4, 5, 6 455; CHECK-NEXT: or 3, 3, 4 456; CHECK-NEXT: cntlzw 3, 3 457; CHECK-NEXT: srwi 3, 3, 5 458; CHECK-NEXT: xori 3, 3, 1 459; CHECK-NEXT: blr 460 %cmp1 = icmp ne i32 %a, %b 461 %cmp2 = icmp ne i32 %c, %d 462 %or = or i1 %cmp1, %cmp2 463 ret i1 %or 464} 465 466; This should not be transformed because vector compares + bitwise logic are faster. 467 468define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { 469; CHECK-LABEL: and_eq_vec: 470; CHECK: # %bb.0: 471; CHECK-NEXT: vcmpequw 2, 2, 3 472; CHECK-NEXT: vcmpequw 3, 4, 5 473; CHECK-NEXT: xxland 34, 34, 35 474; CHECK-NEXT: blr 475 %cmp1 = icmp eq <4 x i32> %a, %b 476 %cmp2 = icmp eq <4 x i32> %c, %d 477 %and = and <4 x i1> %cmp1, %cmp2 478 ret <4 x i1> %and 479} 480 481define i1 @or_icmps_const_1bit_diff(i64 %x) { 482; CHECK-LABEL: or_icmps_const_1bit_diff: 483; CHECK: # %bb.0: 484; CHECK-NEXT: addi 3, 3, -13 485; CHECK-NEXT: rldicl 3, 3, 61, 1 486; CHECK-NEXT: rotldi 3, 3, 3 487; CHECK-NEXT: cntlzd 3, 3 488; CHECK-NEXT: rldicl 3, 3, 58, 63 489; CHECK-NEXT: blr 490 %a = icmp eq i64 %x, 17 491 %b = icmp eq i64 %x, 13 492 %r = or i1 %a, %b 493 ret i1 %r 494} 495 496define i1 @and_icmps_const_1bit_diff(i32 %x) { 497; CHECK-LABEL: and_icmps_const_1bit_diff: 498; CHECK: # %bb.0: 499; CHECK-NEXT: addi 3, 3, -4625 500; CHECK-NEXT: rlwinm 3, 3, 0, 28, 26 501; CHECK-NEXT: cntlzw 3, 3 502; CHECK-NEXT: not 3, 3 503; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 504; CHECK-NEXT: blr 505 %a = icmp ne i32 %x, 4625 506 %b = icmp ne i32 %x, 4641 507 %r = and i1 %a, %b 508 ret i1 %r 509} 510 511