1# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s 2# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s --check-prefix=CHECK-LATE 3--- | 4 ; ModuleID = 'rlwinm_rldicl_to_andi.ll' 5 source_filename = "rlwinm_rldicl_to_andi.c" 6 target datalayout = "e-m:e-i64:64-n32:64" 7 target triple = "powerpc64le-unknown-linux-gnu" 8 9 ; Function Attrs: norecurse nounwind readnone 10 define signext i32 @testRLWINMSingleUseDef(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { 11 entry: 12 %shl.mask = and i32 %a, 1048575 13 %tobool = icmp eq i32 %shl.mask, 0 14 %cond = select i1 %tobool, i32 %a, i32 %b 15 ret i32 %cond 16 } 17 18 ; Function Attrs: norecurse nounwind readnone 19 define signext i32 @testRLWINMNoGPRUseZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { 20 entry: 21 %shl.mask = and i32 %a, 1048575 22 %tobool = icmp eq i32 %shl.mask, 0 23 %cond = select i1 %tobool, i32 %a, i32 %b 24 ret i32 %cond 25 } 26 27 ; Function Attrs: norecurse nounwind readnone 28 define signext i32 @testRLWINMNoGPRUseNonZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { 29 entry: 30 %shl.mask = and i32 %a, 1048575 31 %tobool = icmp eq i32 %shl.mask, 0 32 %cond = select i1 %tobool, i32 %a, i32 %b 33 ret i32 %cond 34 } 35 36 ; Function Attrs: norecurse nounwind readnone 37 define i64 @testRLDICLSingleUseDef(i64 %a, i64 %b) local_unnamed_addr #0 { 38 entry: 39 %shl.mask = and i64 %a, 4503599627370495 40 %tobool = icmp eq i64 %shl.mask, 0 41 %cond = select i1 %tobool, i64 %a, i64 %b 42 ret i64 %cond 43 } 44 45 ; Function Attrs: norecurse nounwind readnone 46 define i64 @testRLDICLNoGPRUseZero(i64 %a, i64 %b) local_unnamed_addr #0 { 47 entry: 48 %shl.mask = and i64 %a, 4503599627370495 49 %tobool = icmp eq i64 %shl.mask, 0 50 %cond = select i1 %tobool, i64 %a, i64 %b 51 ret i64 %cond 52 } 53 54 ; Function Attrs: norecurse nounwind readnone 55 define i64 @testRLDICLNoGPRUseNonZero(i64 %a, i64 %b) local_unnamed_addr #0 { 56 entry: 57 %shl.mask = and i64 %a, 4503599627370495 58 %tobool = icmp eq i64 %shl.mask, 0 59 %cond = select i1 %tobool, i64 %a, i64 %b 60 ret i64 %cond 61 } 62 63 attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } 64 65 !llvm.module.flags = !{!0, !1} 66 !llvm.ident = !{!2} 67 68 !0 = !{i32 1, !"wchar_size", i32 4} 69 !1 = !{i32 7, !"PIC Level", i32 2} 70 !2 = !{!"clang version 7.0.0 (trunk 322378)"} 71 72... 73--- 74name: testRLWINMSingleUseDef 75# CHECK: testRLWINMSingleUseDef 76# CHECK-LATE: testRLWINMSingleUseDef 77alignment: 16 78exposesReturnsTwice: false 79legalized: false 80regBankSelected: false 81selected: false 82tracksRegLiveness: true 83registers: 84 - { id: 0, class: g8rc, preferred-register: '' } 85 - { id: 1, class: g8rc, preferred-register: '' } 86 - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } 87 - { id: 3, class: gprc, preferred-register: '' } 88 - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } 89 - { id: 5, class: crrc, preferred-register: '' } 90 - { id: 6, class: gprc, preferred-register: '' } 91 - { id: 7, class: g8rc, preferred-register: '' } 92liveins: 93 - { reg: '$x3', virtual-reg: '%0' } 94 - { reg: '$x4', virtual-reg: '%1' } 95frameInfo: 96 isFrameAddressTaken: false 97 isReturnAddressTaken: false 98 hasStackMap: false 99 hasPatchPoint: false 100 stackSize: 0 101 offsetAdjustment: 0 102 maxAlignment: 0 103 adjustsStack: false 104 hasCalls: false 105 stackProtector: '' 106 maxCallFrameSize: 4294967295 107 hasOpaqueSPAdjustment: false 108 hasVAStart: false 109 hasMustTailInVarArgFunc: false 110 savePoint: '' 111 restorePoint: '' 112fixedStack: 113stack: 114constants: 115body: | 116 bb.0.entry: 117 liveins: $x3, $x4 118 119 %1:g8rc = COPY $x4 120 %0:g8rc = COPY $x3 121 %2:gprc_and_gprc_nor0 = COPY %1.sub_32 122 %3:gprc = LI -11 123 %4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0 124 ; CHECK: LI 4055 125 ; CHECK: ANDI_rec killed %3, 4055 126 ; CHECK-LATE-NOT: andi. 127 ; CHECK-LATE: rlwinm. 128 %5:crrc = COPY killed $cr0 129 %6:gprc = ISEL %4, %2, %5.sub_eq 130 %7:g8rc = EXTSW_32_64 killed %6 131 $x3 = COPY %7 132 BLR8 implicit $lr8, implicit $rm, implicit $x3 133 134... 135--- 136name: testRLWINMNoGPRUseZero 137alignment: 16 138exposesReturnsTwice: false 139legalized: false 140regBankSelected: false 141selected: false 142tracksRegLiveness: true 143registers: 144 - { id: 0, class: g8rc, preferred-register: '' } 145 - { id: 1, class: g8rc, preferred-register: '' } 146 - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } 147 - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } 148 - { id: 4, class: gprc, preferred-register: '' } 149 - { id: 5, class: crrc, preferred-register: '' } 150 - { id: 6, class: gprc, preferred-register: '' } 151 - { id: 7, class: g8rc, preferred-register: '' } 152liveins: 153 - { reg: '$x3', virtual-reg: '%0' } 154 - { reg: '$x4', virtual-reg: '%1' } 155frameInfo: 156 isFrameAddressTaken: false 157 isReturnAddressTaken: false 158 hasStackMap: false 159 hasPatchPoint: false 160 stackSize: 0 161 offsetAdjustment: 0 162 maxAlignment: 0 163 adjustsStack: false 164 hasCalls: false 165 stackProtector: '' 166 maxCallFrameSize: 4294967295 167 hasOpaqueSPAdjustment: false 168 hasVAStart: false 169 hasMustTailInVarArgFunc: false 170 savePoint: '' 171 restorePoint: '' 172fixedStack: 173stack: 174constants: 175body: | 176 bb.0.entry: 177 liveins: $x3, $x4 178 179 %1:g8rc = COPY $x4 180 %0:g8rc = COPY $x3 181 %2:gprc_and_gprc_nor0 = COPY %1.sub_32 182 %3:gprc_and_gprc_nor0 = LI 1 183 %4:gprc = RLWINM_rec %3, 21, 20, 31, implicit-def $cr0 184 ; CHECK: LI 1 185 ; CHECK: ANDI_rec %3, 0 186 ; CHECK-LATE: li [[IMM:[0-9]+]], 1 187 ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0 188 %5:crrc = COPY killed $cr0 189 %6:gprc = ISEL %3, %2, %5.sub_eq 190 %7:g8rc = EXTSW_32_64 killed %6 191 $x3 = COPY %7 192 BLR8 implicit $lr8, implicit $rm, implicit $x3 193 194... 195--- 196name: testRLWINMNoGPRUseNonZero 197alignment: 16 198exposesReturnsTwice: false 199legalized: false 200regBankSelected: false 201selected: false 202tracksRegLiveness: true 203registers: 204 - { id: 0, class: g8rc, preferred-register: '' } 205 - { id: 1, class: g8rc, preferred-register: '' } 206 - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } 207 - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } 208 - { id: 4, class: gprc, preferred-register: '' } 209 - { id: 5, class: crrc, preferred-register: '' } 210 - { id: 6, class: gprc, preferred-register: '' } 211 - { id: 7, class: g8rc, preferred-register: '' } 212liveins: 213 - { reg: '$x3', virtual-reg: '%0' } 214 - { reg: '$x4', virtual-reg: '%1' } 215frameInfo: 216 isFrameAddressTaken: false 217 isReturnAddressTaken: false 218 hasStackMap: false 219 hasPatchPoint: false 220 stackSize: 0 221 offsetAdjustment: 0 222 maxAlignment: 0 223 adjustsStack: false 224 hasCalls: false 225 stackProtector: '' 226 maxCallFrameSize: 4294967295 227 hasOpaqueSPAdjustment: false 228 hasVAStart: false 229 hasMustTailInVarArgFunc: false 230 savePoint: '' 231 restorePoint: '' 232fixedStack: 233stack: 234constants: 235body: | 236 bb.0.entry: 237 liveins: $x3, $x4 238 239 %1:g8rc = COPY $x4 240 %0:g8rc = COPY $x3 241 %2:gprc_and_gprc_nor0 = COPY %1.sub_32 242 %3:gprc_and_gprc_nor0 = LI -11 243 %4:gprc = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0 244 ; CHECK: LI -11 245 ; CHECK: ANDI_rec %3, 65525 246 ; CHECK-LATE-NOT: andi. 247 ; CHECK-LATE: rlwinm. 248 %5:crrc = COPY killed $cr0 249 %6:gprc = ISEL %3, %2, %5.sub_eq 250 %7:g8rc = EXTSW_32_64 killed %6 251 $x3 = COPY %7 252 BLR8 implicit $lr8, implicit $rm, implicit $x3 253 254... 255--- 256name: testRLDICLSingleUseDef 257alignment: 16 258exposesReturnsTwice: false 259legalized: false 260regBankSelected: false 261selected: false 262tracksRegLiveness: true 263registers: 264 - { id: 0, class: g8rc, preferred-register: '' } 265 - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } 266 - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' } 267 - { id: 3, class: crrc, preferred-register: '' } 268 - { id: 4, class: g8rc, preferred-register: '' } 269liveins: 270 - { reg: '$x3', virtual-reg: '%0' } 271 - { reg: '$x4', virtual-reg: '%1' } 272frameInfo: 273 isFrameAddressTaken: false 274 isReturnAddressTaken: false 275 hasStackMap: false 276 hasPatchPoint: false 277 stackSize: 0 278 offsetAdjustment: 0 279 maxAlignment: 0 280 adjustsStack: false 281 hasCalls: false 282 stackProtector: '' 283 maxCallFrameSize: 4294967295 284 hasOpaqueSPAdjustment: false 285 hasVAStart: false 286 hasMustTailInVarArgFunc: false 287 savePoint: '' 288 restorePoint: '' 289fixedStack: 290stack: 291constants: 292body: | 293 bb.0.entry: 294 liveins: $x3, $x4 295 296 %1:g8rc_and_g8rc_nox0 = COPY $x4 297 %0:g8rc = LI8 -11 298 %2:g8rc_and_g8rc_nox0 = RLDICL_rec %0, 2, 49, implicit-def $cr0 299 ; CHECK: LI8 32727 300 ; CHECK: ANDI8_rec killed %0, 32727 301 ; CHECK-LATE-NOT: andi. 302 ; CHECK-LATE: rldicl. 303 %3:crrc = COPY killed $cr0 304 %4:g8rc = ISEL8 %2, %1, %3.sub_eq 305 $x3 = COPY %4 306 BLR8 implicit $lr8, implicit $rm, implicit $x3 307 308... 309--- 310name: testRLDICLNoGPRUseZero 311alignment: 16 312exposesReturnsTwice: false 313legalized: false 314regBankSelected: false 315selected: false 316tracksRegLiveness: true 317registers: 318 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } 319 - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } 320 - { id: 2, class: g8rc, preferred-register: '' } 321 - { id: 3, class: crrc, preferred-register: '' } 322 - { id: 4, class: g8rc, preferred-register: '' } 323liveins: 324 - { reg: '$x3', virtual-reg: '%0' } 325 - { reg: '$x4', virtual-reg: '%1' } 326frameInfo: 327 isFrameAddressTaken: false 328 isReturnAddressTaken: false 329 hasStackMap: false 330 hasPatchPoint: false 331 stackSize: 0 332 offsetAdjustment: 0 333 maxAlignment: 0 334 adjustsStack: false 335 hasCalls: false 336 stackProtector: '' 337 maxCallFrameSize: 4294967295 338 hasOpaqueSPAdjustment: false 339 hasVAStart: false 340 hasMustTailInVarArgFunc: false 341 savePoint: '' 342 restorePoint: '' 343fixedStack: 344stack: 345constants: 346body: | 347 bb.0.entry: 348 liveins: $x3, $x4 349 350 %1:g8rc_and_g8rc_nox0 = COPY $x4 351 %0:g8rc_and_g8rc_nox0 = LI8 1 352 %2:g8rc = RLDICL_rec %0, 32, 33, implicit-def $cr0 353 ; CHECK: LI8 1 354 ; CHECK: ANDI8_rec %0, 0 355 ; CHECK-LATE: li [[IMM:[0-9]+]], 1 356 ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0 357 %3:crrc = COPY killed $cr0 358 %4:g8rc = ISEL8 %0, %1, %3.sub_eq 359 $x3 = COPY %4 360 BLR8 implicit $lr8, implicit $rm, implicit $x3 361 362... 363--- 364name: testRLDICLNoGPRUseNonZero 365alignment: 16 366exposesReturnsTwice: false 367legalized: false 368regBankSelected: false 369selected: false 370tracksRegLiveness: true 371registers: 372 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } 373 - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } 374 - { id: 2, class: g8rc, preferred-register: '' } 375 - { id: 3, class: crrc, preferred-register: '' } 376 - { id: 4, class: g8rc, preferred-register: '' } 377liveins: 378 - { reg: '$x3', virtual-reg: '%0' } 379 - { reg: '$x4', virtual-reg: '%1' } 380frameInfo: 381 isFrameAddressTaken: false 382 isReturnAddressTaken: false 383 hasStackMap: false 384 hasPatchPoint: false 385 stackSize: 0 386 offsetAdjustment: 0 387 maxAlignment: 0 388 adjustsStack: false 389 hasCalls: false 390 stackProtector: '' 391 maxCallFrameSize: 4294967295 392 hasOpaqueSPAdjustment: false 393 hasVAStart: false 394 hasMustTailInVarArgFunc: false 395 savePoint: '' 396 restorePoint: '' 397fixedStack: 398stack: 399constants: 400body: | 401 bb.0.entry: 402 liveins: $x3, $x4 403 404 %1:g8rc_and_g8rc_nox0 = COPY $x4 405 %0:g8rc_and_g8rc_nox0 = LI8 -11 406 %2:g8rc = RLDICL_rec %0, 2, 49, implicit-def $cr0 407 ; CHECK: LI8 -11 408 ; CHECK: ANDI8_rec %0, 65525 409 ; CHECK-LATE-NOT: andi. 410 ; CHECK-LATE: rldicl. 411 %3:crrc = COPY killed $cr0 412 %4:g8rc = ISEL8 %0, %1, %3.sub_eq 413 $x3 = COPY %4 414 BLR8 implicit $lr8, implicit $rm, implicit $x3 415 416... 417