xref: /llvm-project/llvm/test/CodeGen/PowerPC/rlwinm.ll (revision 65ae09eeb6773b14189fc67051870c8fc4eb9ae3) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
3
4define i32 @test1(i32 %a) {
5; CHECK-LABEL: test1:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    rlwinm 3, 3, 0, 4, 19
8; CHECK-NEXT:    blr
9entry:
10  %tmp.1 = and i32 %a, 268431360
11  ret i32 %tmp.1
12}
13
14define i32 @test2(i32 %a) {
15; CHECK-LABEL: test2:
16; CHECK:       # %bb.0: # %entry
17; CHECK-NEXT:    rlwinm 3, 3, 24, 24, 31
18; CHECK-NEXT:    blr
19entry:
20  %tmp.2 = ashr i32 %a, 8
21  %tmp.3 = and i32 %tmp.2, 255
22  ret i32 %tmp.3
23}
24
25define i32 @test3(i32 %a) {
26; CHECK-LABEL: test3:
27; CHECK:       # %bb.0: # %entry
28; CHECK-NEXT:    rlwinm 3, 3, 24, 24, 31
29; CHECK-NEXT:    blr
30entry:
31  %tmp.3 = lshr i32 %a, 8
32  %tmp.4 = and i32 %tmp.3, 255
33  ret i32 %tmp.4
34}
35
36define i32 @test4(i32 %a) {
37; CHECK-LABEL: test4:
38; CHECK:       # %bb.0: # %entry
39; CHECK-NEXT:    rlwinm 3, 3, 8, 0, 8
40; CHECK-NEXT:    blr
41entry:
42  %tmp.2 = shl i32 %a, 8
43  %tmp.3 = and i32 %tmp.2, -8388608
44  ret i32 %tmp.3
45}
46
47define i32 @test5(i32 %a) {
48; CHECK-LABEL: test5:
49; CHECK:       # %bb.0: # %entry
50; CHECK-NEXT:    rlwinm 3, 3, 24, 24, 31
51; CHECK-NEXT:    blr
52entry:
53  %tmp.1 = and i32 %a, 65280
54  %tmp.2 = ashr i32 %tmp.1, 8
55  ret i32 %tmp.2
56}
57
58define i32 @test6(i32 %a) {
59; CHECK-LABEL: test6:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    rlwinm 3, 3, 24, 24, 31
62; CHECK-NEXT:    blr
63entry:
64  %tmp.1 = and i32 %a, 65280
65  %tmp.2 = lshr i32 %tmp.1, 8
66  ret i32 %tmp.2
67}
68
69define i32 @test7(i32 %a) {
70; CHECK-LABEL: test7:
71; CHECK:       # %bb.0: # %entry
72; CHECK-NEXT:    rlwinm 3, 3, 8, 0, 7
73; CHECK-NEXT:    blr
74entry:
75  %tmp.1 = and i32 %a, 16711680
76  %tmp.2 = shl i32 %tmp.1, 8
77  ret i32 %tmp.2
78}
79
80define i32 @test8(i32 %a, i32 %s) {
81; CHECK-LABEL: test8:
82; CHECK:       # %bb.0: # %entry
83; CHECK-NEXT:    rlwnm 3, 3, 4, 23, 31
84; CHECK-NEXT:    blr
85entry:
86  %r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 %s, i32 511)
87  ret i32 %r
88}
89
90define i32 @test9(i32 %a) {
91; CHECK-LABEL: test9:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    rlwinm 3, 3, 31, 23, 31
94; CHECK-NEXT:    blr
95entry:
96  %r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 31, i32 511)
97  ret i32 %r
98}
99
100define i32 @test10(i32 %a, i32 %s) {
101; CHECK-LABEL: test10:
102; CHECK:       # %bb.0: # %entry
103; CHECK-NEXT:    li 3, 0
104; CHECK-NEXT:    blr
105entry:
106  %r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 %s, i32 0)
107  ret i32 %r
108}
109
110define i32 @test11(i32 %a, i32 %s) {
111; CHECK-LABEL: test11:
112; CHECK:       # %bb.0: # %entry
113; CHECK-NEXT:    rotlw 3, 3, 4
114; CHECK-NEXT:    blr
115entry:
116  %r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 %s, i32 -1)
117  ret i32 %r
118}
119
120declare i32 @llvm.ppc.rlwnm(i32, i32, i32 immarg)
121