1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s 3 4; Check if this causes infinite loop when estimation disabled 5define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) { 6; CHECK-LABEL: repeated_fp_divisor_noest: 7; CHECK: # %bb.0: 8; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha 9; CHECK-NEXT: xscvdpspn 0, 1 10; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l 11; CHECK-NEXT: lxvd2x 1, 0, 3 12; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha 13; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l 14; CHECK-NEXT: lxvd2x 2, 0, 3 15; CHECK-NEXT: xxspltw 0, 0, 0 16; CHECK-NEXT: xvdivsp 0, 2, 0 17; CHECK-NEXT: xxswapd 35, 1 18; CHECK-NEXT: xvmulsp 1, 34, 35 19; CHECK-NEXT: xvmulsp 34, 1, 0 20; CHECK-NEXT: blr 21 %ins = insertelement <4 x float> undef, float %a, i32 0 22 %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer 23 %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000> 24 %mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat 25 ret <4 x float> %mul 26} 27 28define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) { 29; CHECK-LABEL: repeated_fp_divisor: 30; CHECK: # %bb.0: 31; CHECK-NEXT: xscvdpspn 0, 1 32; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha 33; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l 34; CHECK-NEXT: lxvd2x 1, 0, 3 35; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha 36; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l 37; CHECK-NEXT: xxspltw 0, 0, 0 38; CHECK-NEXT: xvresp 2, 0 39; CHECK-NEXT: xxswapd 35, 1 40; CHECK-NEXT: lxvd2x 1, 0, 3 41; CHECK-NEXT: xvmaddasp 1, 0, 2 42; CHECK-NEXT: xvmulsp 0, 34, 35 43; CHECK-NEXT: xvnmsubasp 2, 2, 1 44; CHECK-NEXT: xvmulsp 34, 0, 2 45; CHECK-NEXT: blr 46 %ins = insertelement <4 x float> undef, float %a, i32 0 47 %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer 48 %t1 = fmul contract reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000> 49 %mul = fdiv contract reassoc arcp nsz ninf <4 x float> %t1, %splat 50 ret <4 x float> %mul 51} 52 53