xref: /llvm-project/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir (revision 2432d80d3b54f67c0e496d6b8c11ceb9f573982d) 
1# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=prologepilog -ppc-enable-pe-vector-spills %s -o - | FileCheck %s
2
3---
4name:            test1BB
5alignment:       16
6tracksRegLiveness: true
7liveins:
8body:             |
9  bb.0.entry:
10    $r14 = IMPLICIT_DEF
11    $r15 = IMPLICIT_DEF
12    $r16 = IMPLICIT_DEF
13    $f0 = IMPLICIT_DEF
14    $v20 = IMPLICIT_DEF
15    BLR8 implicit undef $lr8, implicit undef $rm
16
17# Use mtvsrdd to save two GPRs in a single instruction
18# CHECK-LABEL: name:            test1BB
19# CHECK: body:             |
20# CHECK:      liveins: $x14, $x15, $x16, $v20
21# CHECK: $v0 = MTVSRDD killed $x14, killed $x15
22# CHECK-NEXT: $vf1 = MTVSRD killed $x16
23# CHECK: $x16 = MFVSRD killed $vf1
24# CHECK-NEXT: $x15 = MFVSRLD $v0
25# CHECK-NEXT: $x14 = MFVSRD killed $vf0
26...
27
28---
29name:            test2BBs
30alignment:       16
31tracksRegLiveness: true
32liveins:
33body:             |
34  bb.0.entry:
35    successors: %bb.1, %bb.2
36
37    $cr0 = IMPLICIT_DEF
38    BCC 4, killed renamable $cr0, %bb.2
39    B %bb.1
40
41  bb.1:
42    $r14 = IMPLICIT_DEF
43    $r15 = IMPLICIT_DEF
44    $r16 = IMPLICIT_DEF
45    $r3 = IMPLICIT_DEF
46    B %bb.3
47
48  bb.2:
49    $r3 = IMPLICIT_DEF
50
51  bb.3:
52    BLR8 implicit undef $lr8, implicit undef $rm
53
54## The spilled-to registers have to be marked as live-in so that they will not be
55## clobbered before restored in the epilogue.
56# CHECK-LABEL: name:            test2BB
57# CHECK: body:             |
58# CHECK:        $v0 = MTVSRDD killed $x14, killed $x15
59# CHECK-NEXT:   $vf1 = MTVSRD killed $x16
60# CHECK:      bb.2:
61# CHECK-NEXT:   successors: %bb.3
62# CHECK-NEXT:   liveins: $v0, $v1
63# CHECK:      bb.3:
64# CHECK-NEXT:   liveins: $v0, $v1
65# CHECK:        $x16 = MFVSRD killed $vf1
66# CHECK-NEXT:   $x15 = MFVSRLD $v0
67# CHECK-NEXT:   $x14 = MFVSRD killed $vf0
68...
69