xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr59074.ll (revision 032014ef103157bfd8403418538e25f3f58efa9d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE64
3; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE32
4; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE64
5; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE32
6
7; To verify this doesn't crash due to array out of bound.
8define void @pr59074(ptr %0) {
9; LE64-LABEL: pr59074:
10; LE64:       # %bb.0: # %entry
11; LE64-NEXT:    lwz 6, 0(3)
12; LE64-NEXT:    li 7, 12
13; LE64-NEXT:    ld 4, 16(3)
14; LE64-NEXT:    ld 5, 24(3)
15; LE64-NEXT:    addi 6, 6, -12
16; LE64-NEXT:    std 4, 16(3)
17; LE64-NEXT:    std 5, 24(3)
18; LE64-NEXT:    srd 6, 7, 6
19; LE64-NEXT:    li 7, 0
20; LE64-NEXT:    std 7, 8(3)
21; LE64-NEXT:    std 6, 0(3)
22; LE64-NEXT:    blr
23;
24; LE32-LABEL: pr59074:
25; LE32:       # %bb.0: # %entry
26; LE32-NEXT:    stwu 1, -80(1)
27; LE32-NEXT:    .cfi_def_cfa_offset 80
28; LE32-NEXT:    lwz 4, 0(3)
29; LE32-NEXT:    xxlxor 0, 0, 0
30; LE32-NEXT:    li 5, 4
31; LE32-NEXT:    addi 6, 1, 16
32; LE32-NEXT:    li 7, 0
33; LE32-NEXT:    li 8, 12
34; LE32-NEXT:    xxswapd 0, 0
35; LE32-NEXT:    rlwimi 5, 6, 0, 30, 28
36; LE32-NEXT:    stw 7, 44(1)
37; LE32-NEXT:    addi 4, 4, -12
38; LE32-NEXT:    stw 7, 40(1)
39; LE32-NEXT:    stw 7, 36(1)
40; LE32-NEXT:    stw 8, 16(1)
41; LE32-NEXT:    rlwinm 9, 4, 29, 28, 29
42; LE32-NEXT:    stxvd2x 0, 0, 5
43; LE32-NEXT:    clrlwi 4, 4, 27
44; LE32-NEXT:    lwzux 5, 9, 6
45; LE32-NEXT:    lwz 6, 8(9)
46; LE32-NEXT:    lwz 7, 4(9)
47; LE32-NEXT:    lwz 8, 12(9)
48; LE32-NEXT:    xori 9, 4, 31
49; LE32-NEXT:    subfic 11, 4, 32
50; LE32-NEXT:    srw 5, 5, 4
51; LE32-NEXT:    slwi 10, 6, 1
52; LE32-NEXT:    srw 6, 6, 4
53; LE32-NEXT:    slw 9, 10, 9
54; LE32-NEXT:    srw 10, 7, 4
55; LE32-NEXT:    slw 7, 7, 11
56; LE32-NEXT:    slw 11, 8, 11
57; LE32-NEXT:    srw 4, 8, 4
58; LE32-NEXT:    or 5, 7, 5
59; LE32-NEXT:    or 6, 11, 6
60; LE32-NEXT:    or 7, 10, 9
61; LE32-NEXT:    stw 4, 12(3)
62; LE32-NEXT:    stw 6, 8(3)
63; LE32-NEXT:    stw 5, 0(3)
64; LE32-NEXT:    stw 7, 4(3)
65; LE32-NEXT:    addi 1, 1, 80
66; LE32-NEXT:    blr
67;
68; BE64-LABEL: pr59074:
69; BE64:       # %bb.0: # %entry
70; BE64-NEXT:    lwz 6, 12(3)
71; BE64-NEXT:    li 7, 12
72; BE64-NEXT:    ld 4, 24(3)
73; BE64-NEXT:    ld 5, 16(3)
74; BE64-NEXT:    addi 6, 6, -12
75; BE64-NEXT:    std 4, 24(3)
76; BE64-NEXT:    std 5, 16(3)
77; BE64-NEXT:    srd 6, 7, 6
78; BE64-NEXT:    li 7, 0
79; BE64-NEXT:    std 7, 0(3)
80; BE64-NEXT:    std 6, 8(3)
81; BE64-NEXT:    blr
82;
83; BE32-LABEL: pr59074:
84; BE32:       # %bb.0: # %entry
85; BE32-NEXT:    lwz 4, 12(3)
86; BE32-NEXT:    xxlxor 0, 0, 0
87; BE32-NEXT:    addi 5, 1, -64
88; BE32-NEXT:    li 6, 12
89; BE32-NEXT:    li 7, 0
90; BE32-NEXT:    addi 8, 1, -48
91; BE32-NEXT:    stxvw4x 0, 0, 5
92; BE32-NEXT:    stw 6, -36(1)
93; BE32-NEXT:    addi 4, 4, -12
94; BE32-NEXT:    stw 7, -40(1)
95; BE32-NEXT:    stw 7, -44(1)
96; BE32-NEXT:    stw 7, -48(1)
97; BE32-NEXT:    rlwinm 9, 4, 29, 28, 29
98; BE32-NEXT:    clrlwi 4, 4, 27
99; BE32-NEXT:    sub 5, 8, 9
100; BE32-NEXT:    lwz 6, 4(5)
101; BE32-NEXT:    lwz 7, 0(5)
102; BE32-NEXT:    lwz 8, 12(5)
103; BE32-NEXT:    lwz 5, 8(5)
104; BE32-NEXT:    subfic 10, 4, 32
105; BE32-NEXT:    srw 9, 6, 4
106; BE32-NEXT:    slw 11, 7, 10
107; BE32-NEXT:    srw 8, 8, 4
108; BE32-NEXT:    slw 6, 6, 10
109; BE32-NEXT:    slw 10, 5, 10
110; BE32-NEXT:    srw 5, 5, 4
111; BE32-NEXT:    srw 4, 7, 4
112; BE32-NEXT:    or 7, 11, 9
113; BE32-NEXT:    or 8, 10, 8
114; BE32-NEXT:    or 5, 6, 5
115; BE32-NEXT:    stw 4, 0(3)
116; BE32-NEXT:    stw 5, 8(3)
117; BE32-NEXT:    stw 8, 12(3)
118; BE32-NEXT:    stw 7, 4(3)
119; BE32-NEXT:    blr
120entry:
121  %v1 = load <2 x i128>, <2 x i128>* %0
122  %v2 = insertelement <2 x i128> %v1, i128 12, i32 0
123  %v3 = sub <2 x i128> %v1, %v2
124  %v4 = lshr <2 x i128> %v2, %v3
125  store <2 x i128> %v4, <2 x i128>* %0
126  ret void
127}
128