xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr48388.ll (revision b922a3621116b404d868af8b74cab25ab78555be)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -ppc-asm-full-reg-names \
3; RUN:   < %s | FileCheck %s
4
5define i64 @julia_div_i64(i64 %0, i64 %1) local_unnamed_addr #0 {
6; CHECK-LABEL: julia_div_i64:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    divd r5, r3, r4
9; CHECK-NEXT:    lis r6, -1592
10; CHECK-NEXT:    cmpdi r3, 0
11; CHECK-NEXT:    ori r7, r6, 21321
12; CHECK-NEXT:    ori r6, r6, 65519
13; CHECK-NEXT:    rldic r7, r7, 4, 17
14; CHECK-NEXT:    rldic r6, r6, 4, 17
15; CHECK-NEXT:    iselgt r8, r6, r7
16; CHECK-NEXT:    cmpdi r4, 0
17; CHECK-NEXT:    iselgt r6, r6, r7
18; CHECK-NEXT:    xor r6, r8, r6
19; CHECK-NEXT:    cntlzd r6, r6
20; CHECK-NEXT:    rldicl r6, r6, 58, 63
21; CHECK-NEXT:    mulld r4, r5, r4
22; CHECK-NEXT:    xor r3, r4, r3
23; CHECK-NEXT:    addic r4, r3, -1
24; CHECK-NEXT:    subfe r3, r4, r3
25; CHECK-NEXT:    and r3, r6, r3
26; CHECK-NEXT:    add r3, r5, r3
27; CHECK-NEXT:    blr
28entry:
29  %2 = sdiv i64 %0, %1
30  %3 = icmp sgt i64 %0, 0
31  %4 = icmp sgt i64 %1, 0
32  %5 = select i1 %3, i64 140735820070640, i64 140735819363472
33  %6 = select i1 %4, i64 140735820070640, i64 140735819363472
34  %7 = icmp eq i64 %5, %6
35  %8 = mul i64 %2, %1
36  %9 = icmp ne i64 %8, %0
37  %10 = and i1 %7, %9
38  %11 = zext i1 %10 to i64
39  %12 = add i64 %2, %11
40  ret i64 %12
41}
42