1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \ 3; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \ 4; RUN: -check-prefix=CHECK-LE %s 5 6define void @foo(i32 %vla_size) #0 { 7; CHECK-LE-LABEL: foo: 8; CHECK-LE: # %bb.0: # %entry 9; CHECK-LE-NEXT: clrldi r12, r1, 53 10; CHECK-LE-NEXT: std r31, -8(r1) 11; CHECK-LE-NEXT: std r30, -16(r1) 12; CHECK-LE-NEXT: mr r30, r1 13; CHECK-LE-NEXT: sub r0, r1, r12 14; CHECK-LE-NEXT: li r12, -6144 15; CHECK-LE-NEXT: add r0, r12, r0 16; CHECK-LE-NEXT: sub r12, r0, r1 17; CHECK-LE-NEXT: cmpdi r12, -4096 18; CHECK-LE-NEXT: bge cr0, .LBB0_2 19; CHECK-LE-NEXT: .LBB0_1: # %entry 20; CHECK-LE-NEXT: # 21; CHECK-LE-NEXT: stdu r30, -4096(r1) 22; CHECK-LE-NEXT: addi r12, r12, 4096 23; CHECK-LE-NEXT: cmpdi r12, -4096 24; CHECK-LE-NEXT: blt cr0, .LBB0_1 25; CHECK-LE-NEXT: .LBB0_2: # %entry 26; CHECK-LE-NEXT: stdux r30, r1, r12 27; CHECK-LE-NEXT: mr r0, r30 28; CHECK-LE-NEXT: .cfi_def_cfa_register r0 29; CHECK-LE-NEXT: .cfi_def_cfa_register r30 30; CHECK-LE-NEXT: .cfi_offset r31, -8 31; CHECK-LE-NEXT: .cfi_offset r30, -16 32; CHECK-LE-NEXT: clrldi r3, r3, 32 33; CHECK-LE-NEXT: li r4, -2048 34; CHECK-LE-NEXT: li r6, -4096 35; CHECK-LE-NEXT: mr r31, r1 36; CHECK-LE-NEXT: addi r3, r3, 15 37; CHECK-LE-NEXT: rldicl r3, r3, 60, 4 38; CHECK-LE-NEXT: rldicl r3, r3, 4, 31 39; CHECK-LE-NEXT: neg r5, r3 40; CHECK-LE-NEXT: ld r3, 0(r1) 41; CHECK-LE-NEXT: and r4, r5, r4 42; CHECK-LE-NEXT: mr r5, r4 43; CHECK-LE-NEXT: divd r7, r5, r6 44; CHECK-LE-NEXT: add r4, r1, r5 45; CHECK-LE-NEXT: mulld r6, r7, r6 46; CHECK-LE-NEXT: sub r5, r5, r6 47; CHECK-LE-NEXT: stdux r3, r1, r5 48; CHECK-LE-NEXT: cmpd r1, r4 49; CHECK-LE-NEXT: beq cr0, .LBB0_4 50; CHECK-LE-NEXT: .LBB0_3: # %entry 51; CHECK-LE-NEXT: # 52; CHECK-LE-NEXT: stdu r3, -4096(r1) 53; CHECK-LE-NEXT: cmpd r1, r4 54; CHECK-LE-NEXT: bne cr0, .LBB0_3 55; CHECK-LE-NEXT: .LBB0_4: # %entry 56; CHECK-LE-NEXT: addi r3, r1, 2048 57; CHECK-LE-NEXT: lbz r3, 0(r3) 58; CHECK-LE-NEXT: mr r1, r30 59; CHECK-LE-NEXT: ld r31, -8(r1) 60; CHECK-LE-NEXT: ld r30, -16(r1) 61; CHECK-LE-NEXT: blr 62entry: 63 %0 = zext i32 %vla_size to i64 64 %vla = alloca i8, i64 %0, align 2048 65 %1 = load volatile i8, ptr %vla, align 2048 66 ret void 67} 68 69attributes #0 = { "probe-stack"="inline-asm" } 70