xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr45628.ll (revision b922a3621116b404d868af8b74cab25ab78555be) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck  %s \
4; RUN:   -check-prefix=P9-VSX
5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6; RUN:   -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -mattr=-vsx < %s | FileCheck  %s \
7; RUN:   -check-prefix=P9-NOVSX
8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9; RUN:   -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck  %s \
10; RUN:   -check-prefix=P8-VSX
11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12; RUN:   -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -mattr=-vsx < %s | FileCheck  %s \
13; RUN:   -check-prefix=P8-NOVSX
14
15define <1 x i128> @rotl_64(<1 x i128> %num) {
16; P9-VSX-LABEL: rotl_64:
17; P9-VSX:       # %bb.0: # %entry
18; P9-VSX-NEXT:    xxswapd v2, v2
19; P9-VSX-NEXT:    blr
20;
21; P9-NOVSX-LABEL: rotl_64:
22; P9-NOVSX:       # %bb.0: # %entry
23; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 8
24; P9-NOVSX-NEXT:    blr
25;
26; P8-VSX-LABEL: rotl_64:
27; P8-VSX:       # %bb.0: # %entry
28; P8-VSX-NEXT:    xxswapd v2, v2
29; P8-VSX-NEXT:    blr
30;
31; P8-NOVSX-LABEL: rotl_64:
32; P8-NOVSX:       # %bb.0: # %entry
33; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 8
34; P8-NOVSX-NEXT:    blr
35entry:
36  %shl = shl <1 x i128> %num, <i128 64>
37  %shr = lshr <1 x i128> %num, <i128 64>
38  %or = or <1 x i128> %shl, %shr
39  ret <1 x i128> %or
40}
41
42define <1 x i128> @rotl_32(<1 x i128> %num) {
43; P9-VSX-LABEL: rotl_32:
44; P9-VSX:       # %bb.0: # %entry
45; P9-VSX-NEXT:    xxsldwi v2, v2, v2, 3
46; P9-VSX-NEXT:    blr
47;
48; P9-NOVSX-LABEL: rotl_32:
49; P9-NOVSX:       # %bb.0: # %entry
50; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 12
51; P9-NOVSX-NEXT:    blr
52;
53; P8-VSX-LABEL: rotl_32:
54; P8-VSX:       # %bb.0: # %entry
55; P8-VSX-NEXT:    xxsldwi v2, v2, v2, 3
56; P8-VSX-NEXT:    blr
57;
58; P8-NOVSX-LABEL: rotl_32:
59; P8-NOVSX:       # %bb.0: # %entry
60; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 12
61; P8-NOVSX-NEXT:    blr
62entry:
63  %shl = shl <1 x i128> %num, <i128 32>
64  %shr = lshr <1 x i128> %num, <i128 96>
65  %or = or <1 x i128> %shl, %shr
66  ret <1 x i128> %or
67}
68
69define <1 x i128> @rotl_96(<1 x i128> %num) {
70; P9-VSX-LABEL: rotl_96:
71; P9-VSX:       # %bb.0: # %entry
72; P9-VSX-NEXT:    xxsldwi v2, v2, v2, 1
73; P9-VSX-NEXT:    blr
74;
75; P9-NOVSX-LABEL: rotl_96:
76; P9-NOVSX:       # %bb.0: # %entry
77; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 4
78; P9-NOVSX-NEXT:    blr
79;
80; P8-VSX-LABEL: rotl_96:
81; P8-VSX:       # %bb.0: # %entry
82; P8-VSX-NEXT:    xxsldwi v2, v2, v2, 1
83; P8-VSX-NEXT:    blr
84;
85; P8-NOVSX-LABEL: rotl_96:
86; P8-NOVSX:       # %bb.0: # %entry
87; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 4
88; P8-NOVSX-NEXT:    blr
89entry:
90  %shl = shl <1 x i128> %num, <i128 96>
91  %shr = lshr <1 x i128> %num, <i128 32>
92  %or = or <1 x i128> %shl, %shr
93  ret <1 x i128> %or
94}
95
96define <1 x i128> @rotl_16(<1 x i128> %num) {
97; P9-VSX-LABEL: rotl_16:
98; P9-VSX:       # %bb.0: # %entry
99; P9-VSX-NEXT:    vsldoi v2, v2, v2, 14
100; P9-VSX-NEXT:    blr
101;
102; P9-NOVSX-LABEL: rotl_16:
103; P9-NOVSX:       # %bb.0: # %entry
104; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 14
105; P9-NOVSX-NEXT:    blr
106;
107; P8-VSX-LABEL: rotl_16:
108; P8-VSX:       # %bb.0: # %entry
109; P8-VSX-NEXT:    vsldoi v2, v2, v2, 14
110; P8-VSX-NEXT:    blr
111;
112; P8-NOVSX-LABEL: rotl_16:
113; P8-NOVSX:       # %bb.0: # %entry
114; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 14
115; P8-NOVSX-NEXT:    blr
116entry:
117  %shl = shl <1 x i128> %num, <i128 16>
118  %shr = lshr <1 x i128> %num, <i128 112>
119  %or = or <1 x i128> %shl, %shr
120  ret <1 x i128> %or
121}
122
123define <1 x i128> @rotl_112(<1 x i128> %num) {
124; P9-VSX-LABEL: rotl_112:
125; P9-VSX:       # %bb.0: # %entry
126; P9-VSX-NEXT:    vsldoi v2, v2, v2, 2
127; P9-VSX-NEXT:    blr
128;
129; P9-NOVSX-LABEL: rotl_112:
130; P9-NOVSX:       # %bb.0: # %entry
131; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 2
132; P9-NOVSX-NEXT:    blr
133;
134; P8-VSX-LABEL: rotl_112:
135; P8-VSX:       # %bb.0: # %entry
136; P8-VSX-NEXT:    vsldoi v2, v2, v2, 2
137; P8-VSX-NEXT:    blr
138;
139; P8-NOVSX-LABEL: rotl_112:
140; P8-NOVSX:       # %bb.0: # %entry
141; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 2
142; P8-NOVSX-NEXT:    blr
143entry:
144  %shl = shl <1 x i128> %num, <i128 112>
145  %shr = lshr <1 x i128> %num, <i128 16>
146  %or = or <1 x i128> %shl, %shr
147  ret <1 x i128> %or
148}
149
150define <1 x i128> @rotl_8(<1 x i128> %num) {
151; P9-VSX-LABEL: rotl_8:
152; P9-VSX:       # %bb.0: # %entry
153; P9-VSX-NEXT:    vsldoi v2, v2, v2, 15
154; P9-VSX-NEXT:    blr
155;
156; P9-NOVSX-LABEL: rotl_8:
157; P9-NOVSX:       # %bb.0: # %entry
158; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 15
159; P9-NOVSX-NEXT:    blr
160;
161; P8-VSX-LABEL: rotl_8:
162; P8-VSX:       # %bb.0: # %entry
163; P8-VSX-NEXT:    vsldoi v2, v2, v2, 15
164; P8-VSX-NEXT:    blr
165;
166; P8-NOVSX-LABEL: rotl_8:
167; P8-NOVSX:       # %bb.0: # %entry
168; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 15
169; P8-NOVSX-NEXT:    blr
170entry:
171  %shl = shl <1 x i128> %num, <i128 8>
172  %shr = lshr <1 x i128> %num, <i128 120>
173  %or = or <1 x i128> %shl, %shr
174  ret <1 x i128> %or
175}
176
177define <1 x i128> @rotl_120(<1 x i128> %num) {
178; P9-VSX-LABEL: rotl_120:
179; P9-VSX:       # %bb.0: # %entry
180; P9-VSX-NEXT:    vsldoi v2, v2, v2, 1
181; P9-VSX-NEXT:    blr
182;
183; P9-NOVSX-LABEL: rotl_120:
184; P9-NOVSX:       # %bb.0: # %entry
185; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 1
186; P9-NOVSX-NEXT:    blr
187;
188; P8-VSX-LABEL: rotl_120:
189; P8-VSX:       # %bb.0: # %entry
190; P8-VSX-NEXT:    vsldoi v2, v2, v2, 1
191; P8-VSX-NEXT:    blr
192;
193; P8-NOVSX-LABEL: rotl_120:
194; P8-NOVSX:       # %bb.0: # %entry
195; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 1
196; P8-NOVSX-NEXT:    blr
197entry:
198  %shl = shl <1 x i128> %num, <i128 120>
199  %shr = lshr <1 x i128> %num, <i128 8>
200  %or = or <1 x i128> %shl, %shr
201  ret <1 x i128> %or
202}
203
204define <1 x i128> @rotl_28(<1 x i128> %num) {
205; P9-VSX-LABEL: rotl_28:
206; P9-VSX:       # %bb.0: # %entry
207; P9-VSX-NEXT:    mfvsrld r4, v2
208; P9-VSX-NEXT:    mfvsrd r3, v2
209; P9-VSX-NEXT:    rotldi r5, r4, 28
210; P9-VSX-NEXT:    rldimi r5, r3, 28, 0
211; P9-VSX-NEXT:    rotldi r3, r3, 28
212; P9-VSX-NEXT:    rldimi r3, r4, 28, 0
213; P9-VSX-NEXT:    mtvsrdd v2, r5, r3
214; P9-VSX-NEXT:    blr
215;
216; P9-NOVSX-LABEL: rotl_28:
217; P9-NOVSX:       # %bb.0: # %entry
218; P9-NOVSX-NEXT:    addi r3, r1, -32
219; P9-NOVSX-NEXT:    stvx v2, 0, r3
220; P9-NOVSX-NEXT:    ld r4, -32(r1)
221; P9-NOVSX-NEXT:    ld r3, -24(r1)
222; P9-NOVSX-NEXT:    rotldi r5, r4, 28
223; P9-NOVSX-NEXT:    rldimi r5, r3, 28, 0
224; P9-NOVSX-NEXT:    rotldi r3, r3, 28
225; P9-NOVSX-NEXT:    rldimi r3, r4, 28, 0
226; P9-NOVSX-NEXT:    std r5, -8(r1)
227; P9-NOVSX-NEXT:    std r3, -16(r1)
228; P9-NOVSX-NEXT:    addi r3, r1, -16
229; P9-NOVSX-NEXT:    lvx v2, 0, r3
230; P9-NOVSX-NEXT:    blr
231;
232; P8-VSX-LABEL: rotl_28:
233; P8-VSX:       # %bb.0: # %entry
234; P8-VSX-NEXT:    xxswapd vs0, v2
235; P8-VSX-NEXT:    mfvsrd r4, v2
236; P8-VSX-NEXT:    rotldi r5, r4, 28
237; P8-VSX-NEXT:    mffprd r3, f0
238; P8-VSX-NEXT:    rldimi r5, r3, 28, 0
239; P8-VSX-NEXT:    rotldi r3, r3, 28
240; P8-VSX-NEXT:    rldimi r3, r4, 28, 0
241; P8-VSX-NEXT:    mtfprd f0, r5
242; P8-VSX-NEXT:    mtfprd f1, r3
243; P8-VSX-NEXT:    xxmrghd v2, vs1, vs0
244; P8-VSX-NEXT:    blr
245;
246; P8-NOVSX-LABEL: rotl_28:
247; P8-NOVSX:       # %bb.0: # %entry
248; P8-NOVSX-NEXT:    addi r3, r1, -32
249; P8-NOVSX-NEXT:    stvx v2, 0, r3
250; P8-NOVSX-NEXT:    ld r4, -32(r1)
251; P8-NOVSX-NEXT:    ld r3, -24(r1)
252; P8-NOVSX-NEXT:    rotldi r5, r4, 28
253; P8-NOVSX-NEXT:    rldimi r5, r3, 28, 0
254; P8-NOVSX-NEXT:    rotldi r3, r3, 28
255; P8-NOVSX-NEXT:    rldimi r3, r4, 28, 0
256; P8-NOVSX-NEXT:    std r5, -8(r1)
257; P8-NOVSX-NEXT:    std r3, -16(r1)
258; P8-NOVSX-NEXT:    addi r3, r1, -16
259; P8-NOVSX-NEXT:    lvx v2, 0, r3
260; P8-NOVSX-NEXT:    blr
261entry:
262  %shl = shl <1 x i128> %num, <i128 28>
263  %shr = lshr <1 x i128> %num, <i128 100>
264  %or = or <1 x i128> %shl, %shr
265  ret <1 x i128> %or
266}
267
268define <1 x i128> @NO_rotl(<1 x i128> %num) {
269; P9-VSX-LABEL: NO_rotl:
270; P9-VSX:       # %bb.0: # %entry
271; P9-VSX-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
272; P9-VSX-NEXT:    addi r3, r3, .LCPI8_0@toc@l
273; P9-VSX-NEXT:    lxv v3, 0(r3)
274; P9-VSX-NEXT:    addis r3, r2, .LCPI8_1@toc@ha
275; P9-VSX-NEXT:    addi r3, r3, .LCPI8_1@toc@l
276; P9-VSX-NEXT:    vslo v4, v2, v3
277; P9-VSX-NEXT:    vspltb v3, v3, 15
278; P9-VSX-NEXT:    vsl v3, v4, v3
279; P9-VSX-NEXT:    lxv v4, 0(r3)
280; P9-VSX-NEXT:    vsro v2, v2, v4
281; P9-VSX-NEXT:    vspltb v4, v4, 15
282; P9-VSX-NEXT:    vsr v2, v2, v4
283; P9-VSX-NEXT:    xxlor v2, v3, v2
284; P9-VSX-NEXT:    blr
285;
286; P9-NOVSX-LABEL: NO_rotl:
287; P9-NOVSX:       # %bb.0: # %entry
288; P9-NOVSX-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
289; P9-NOVSX-NEXT:    addi r3, r3, .LCPI8_0@toc@l
290; P9-NOVSX-NEXT:    lvx v3, 0, r3
291; P9-NOVSX-NEXT:    addis r3, r2, .LCPI8_1@toc@ha
292; P9-NOVSX-NEXT:    addi r3, r3, .LCPI8_1@toc@l
293; P9-NOVSX-NEXT:    vslo v4, v2, v3
294; P9-NOVSX-NEXT:    vspltb v3, v3, 15
295; P9-NOVSX-NEXT:    vsl v3, v4, v3
296; P9-NOVSX-NEXT:    lvx v4, 0, r3
297; P9-NOVSX-NEXT:    vsro v2, v2, v4
298; P9-NOVSX-NEXT:    vspltb v4, v4, 15
299; P9-NOVSX-NEXT:    vsr v2, v2, v4
300; P9-NOVSX-NEXT:    vor v2, v3, v2
301; P9-NOVSX-NEXT:    blr
302;
303; P8-VSX-LABEL: NO_rotl:
304; P8-VSX:       # %bb.0: # %entry
305; P8-VSX-NEXT:    xxswapd vs0, v2
306; P8-VSX-NEXT:    mfvsrd r4, v2
307; P8-VSX-NEXT:    mffprd r3, f0
308; P8-VSX-NEXT:    rotldi r5, r3, 20
309; P8-VSX-NEXT:    sldi r3, r3, 20
310; P8-VSX-NEXT:    rldimi r5, r4, 20, 0
311; P8-VSX-NEXT:    mtfprd f0, r3
312; P8-VSX-NEXT:    li r3, 0
313; P8-VSX-NEXT:    mtfprd f1, r5
314; P8-VSX-NEXT:    xxmrghd v2, vs1, vs0
315; P8-VSX-NEXT:    mtfprd f0, r3
316; P8-VSX-NEXT:    rldicl r3, r4, 28, 36
317; P8-VSX-NEXT:    mtfprd f1, r3
318; P8-VSX-NEXT:    xxmrghd v3, vs0, vs1
319; P8-VSX-NEXT:    xxlor v2, v2, v3
320; P8-VSX-NEXT:    blr
321;
322; P8-NOVSX-LABEL: NO_rotl:
323; P8-NOVSX:       # %bb.0: # %entry
324; P8-NOVSX-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
325; P8-NOVSX-NEXT:    addi r3, r3, .LCPI8_0@toc@l
326; P8-NOVSX-NEXT:    lvx v3, 0, r3
327; P8-NOVSX-NEXT:    addis r3, r2, .LCPI8_1@toc@ha
328; P8-NOVSX-NEXT:    addi r3, r3, .LCPI8_1@toc@l
329; P8-NOVSX-NEXT:    lvx v5, 0, r3
330; P8-NOVSX-NEXT:    vslo v4, v2, v3
331; P8-NOVSX-NEXT:    vspltb v3, v3, 15
332; P8-NOVSX-NEXT:    vsl v3, v4, v3
333; P8-NOVSX-NEXT:    vsro v2, v2, v5
334; P8-NOVSX-NEXT:    vspltb v5, v5, 15
335; P8-NOVSX-NEXT:    vsr v2, v2, v5
336; P8-NOVSX-NEXT:    vor v2, v3, v2
337; P8-NOVSX-NEXT:    blr
338entry:
339  %shl = shl <1 x i128> %num, <i128 20>
340  %shr = lshr <1 x i128> %num, <i128 100>
341  %or = or <1 x i128> %shl, %shr
342  ret <1 x i128> %or
343}
344
345define <1 x i128> @shufflevector(<1 x i128> %num) {
346; P9-VSX-LABEL: shufflevector:
347; P9-VSX:       # %bb.0: # %entry
348; P9-VSX-NEXT:    xxswapd v2, v2
349; P9-VSX-NEXT:    blr
350;
351; P9-NOVSX-LABEL: shufflevector:
352; P9-NOVSX:       # %bb.0: # %entry
353; P9-NOVSX-NEXT:    vsldoi v2, v2, v2, 8
354; P9-NOVSX-NEXT:    blr
355;
356; P8-VSX-LABEL: shufflevector:
357; P8-VSX:       # %bb.0: # %entry
358; P8-VSX-NEXT:    xxswapd v2, v2
359; P8-VSX-NEXT:    blr
360;
361; P8-NOVSX-LABEL: shufflevector:
362; P8-NOVSX:       # %bb.0: # %entry
363; P8-NOVSX-NEXT:    vsldoi v2, v2, v2, 8
364; P8-NOVSX-NEXT:    blr
365entry:
366  %0 = bitcast <1 x i128> %num to <2 x i64>
367  %vecins2 = shufflevector <2 x i64> %0, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
368  %1 = bitcast <2 x i64> %vecins2 to <1 x i128>
369  ret <1 x i128> %1
370}
371